search for: nvkm_secboot

...ce.h @@ -24,6 +24,7 @@ enum nvkm_devidx { NVKM_SUBDEV_VOLT, NVKM_SUBDEV_THERM, NVKM_SUBDEV_CLK, + NVKM_SUBDEV_SECBOOT, NVKM_ENGINE_DMAOBJ, NVKM_ENGINE_IFB, @@ -119,6 +120,7 @@ struct nvkm_device { struct nvkm_therm *therm; struct nvkm_timer *timer; struct nvkm_volt *volt; + struct nvkm_secboot *secboot; struct nvkm_engine *bsp; struct nvkm_engine *ce[3]; @@ -184,6 +186,7 @@ struct nvkm_device_chip { int (*therm )(struct nvkm_device *, int idx, struct nvkm_therm **); int (*timer )(struct nvkm_device *, int idx, struct nvkm_timer **); int (*volt )(struct nvkm_device *, int...

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot:

...bdev/secboot.h @@ -30,6 +30,7 @@ * @base: base IO address of the falcon performing secure boot * @managed_falcons: bitfield of falcons managed by this ACR * @debug_mode: whether the debug or production signatures should be used + * @wpr_set: whether the WPR region is currently set */ struct nvkm_secboot { const struct nvkm_secboot_func *func; @@ -44,6 +45,8 @@ struct nvkm_secboot { u32 wpr_size; bool debug_mode; + + bool wpr_set; }; #define nvkm_secboot(p) container_of((p), struct nvkm_secboot, subdev) diff --git a/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drm/nouveau/nvkm/subdev/se...

This series fixes two cases where behavior on secure boot errors could be improved: 1) Patch 2 propages secure-boot errors from GR init, making sure initialization fails as it should. Failure to do so results in a black screen during boot, as reported in FD bug 94990. 2) Patches 3-4 make the absence of required secure firmware files a non-fatal error. The previous behavior was to give up

...fer. Alexandre Courbot (8): core: constify nv*_printk macros mc: add nvkm_mc_enabled() function core: add falcon library functions secboot: use falcon library definitions secboot: use falcon library gr/gf100: split gf100_gr_init_ctxctl() gr/gf100: use falcon library secboot: remove nvkm_secboot_start() drm/nouveau/include/nvkm/core/client.h | 4 +- drm/nouveau/include/nvkm/core/device.h | 5 +- drm/nouveau/include/nvkm/core/subdev.h | 2 +- drm/nouveau/include/nvkm/engine/falcon.h | 77 +++++++- drm/nouveau/include/nvkm/subdev/mc.h | 1 +- drm/nouveau/include/nvk...

...pmu/gk20a: simplify code a bit pmu/gk20a: use falcon library functions gm20b: add dummy PMU device secboot: fix functions definitions secboot: use falcon library gr: add fini() hook gr/gf100: split gf100_gr_init_ctxctl() gr/gf100: instantiate and reserve GR falcons secboot: remove nvkm_secboot_start() drm/nouveau/include/nvkm/core/client.h | 4 +- drm/nouveau/include/nvkm/core/device.h | 3 +- drm/nouveau/include/nvkm/core/subdev.h | 2 +- drm/nouveau/include/nvkm/engine/falcon.h | 65 +++++- drm/nouveau/include/nvkm/subdev/mc.h | 1 +- drm/nouveau/include/nvkm/...

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

Hi Alexandre, On 18 January 2016 at 06:10, Alexandre Courbot <acourbot at nvidia.com> wrote: [snip] > +static const char * > +managed_falcons_names[] = { > + [NVKM_SECBOOT_FALCON_PMU] = "PMU", > + [NVKM_SECBOOT_FALCON_RESERVED] = "<invalid>", "<reserved>" perhaps ? we already have one invalid below. > + [NVKM_SECBOOT_FALCON_FECS] = "FECS", > + [NVKM_SECBOOT_FALCON_GPCCS] = "GPCCS&quo...

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

...v/secboot/gm200.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h > index 62c5e162099a..280b1448df88 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h > @@ -41,6 +41,6 @@ int gm200_secboot_run_blob(struct nvkm_secboot *, struct nvkm_gpuobj *, > struct nvkm_falcon *); > > /* Tegra-only */ > -int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *, u32); > +int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *); > > #endif > diff --git a/drivers/gpu/drm/nouvea...

...drm/nouveau/nvkm/subdev/secboot/gm200.c diff --git a/drm/nouveau/include/nvkm/subdev/secboot.h b/drm/nouveau/include/nvkm/subdev/secboot.h index f40b57567676..a509f2b4aa5f 100644 --- a/drm/nouveau/include/nvkm/subdev/secboot.h +++ b/drm/nouveau/include/nvkm/subdev/secboot.h @@ -53,4 +53,6 @@ bool nvkm_secboot_is_managed(struct nvkm_secboot *, enum nvkm_secboot_falcon); int nvkm_secboot_reset(struct nvkm_secboot *, u32 falcon); int nvkm_secboot_start(struct nvkm_secboot *, u32 falcon); +int gm200_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **); + #endif diff --git a/drm/nouveau/nvkm/e...

...++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/secboot/base.c b/drm/nouveau/nvkm/subdev/secboot/base.c index 520facf9bc07..a4f314803137 100644 --- a/drm/nouveau/nvkm/subdev/secboot/base.c +++ b/drm/nouveau/nvkm/subdev/secboot/base.c @@ -135,7 +135,8 @@ nvkm_secboot_falcon_reset(struct nvkm_secboot *sb) int nvkm_secboot_falcon_run(struct nvkm_secboot *sb) { - struct nvkm_device *device = sb->subdev.device; + struct nvkm_subdev *subdev = &sb->subdev; + struct nvkm_device *device = subdev->device; int ret; /* Start falcon */ @@ -149,11 +150...

...m/nouveau/nvkm/subdev/secboot/gm200.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h index 62c5e162099a..280b1448df88 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h @@ -41,6 +41,6 @@ int gm200_secboot_run_blob(struct nvkm_secboot *, struct nvkm_gpuobj *, struct nvkm_falcon *); /* Tegra-only */ -int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *, u32); +int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/...

...drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h > > index 62c5e162099a..280b1448df88 100644 > > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h > > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h > > @@ -41,6 +41,6 @@ int gm200_secboot_run_blob(struct nvkm_secboot *, struct nvkm_gpuobj *, > > struct nvkm_falcon *); > > > > /* Tegra-only */ > > -int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *, u32); > > +int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *); > > > > #endif >...

...diff --git a/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index a7213542..00095ef8 100644 --- a/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -924,6 +924,19 @@ acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb) } } + /* reset the PMU if needed */ + if (acr->base.boot_falcon == NVKM_SECBOOT_FALCON_PMU && + !nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_PMU)) { + struct nvkm_pmu *pmu = subdev->device->pmu; + if (pmu) { + ret = nvkm_subdev_init(&pmu->subdev); +...