Displaying 6 results from an estimated 6 matches for "nvkm_ram_type_ddr3".
Did you mean:
nvkm_ram_type_gddr3
2015 Sep 29
10
All-round reclocking improvements
In bulletpoints:
- Add some support for G94 and G96 reclocking. Has been tested on literally
two cards, which is hardly adequate as "full coverage". On the other hand,
the changes were small enough to make me confident this might work for others
as well.
- Fix NV50 wait for VBLANK when no monitor is plugged in.
- Voltage related inprovements for GT21x.
- Slightly improve Keplers
2016 Sep 21
8
[PATCH 0/5] GPU-DRM-nouveau: Fine-tuning for five function implementations
From: Markus Elfring <elfring at users.sourceforge.net>
Date: Wed, 21 Sep 2016 09:09:09 +0200
A few update suggestions were taken into account
from static source code analysis.
Markus Elfring (5):
Use kmalloc_array() in nvbios_iccsense_parse()
Use kmalloc_array() in gt215_link_train()
Delete unnecessary braces
Adjust a kzalloc() call in gt215_ram_new()
Add space after an
2016 Sep 21
0
[PATCH 3/5] GPU-DRM-nouveau: Delete unnecessary braces
...struct nvkm_ram *base, u32 freq)
if (!next->bios.ramcfg_DLLoff)
nvkm_sddr2_dll_reset(fuc);
- if (ram->base.type == NVKM_RAM_TYPE_GDDR3) {
+ if (ram->base.type == NVKM_RAM_TYPE_GDDR3)
ram_nsec(fuc, 31000);
- } else {
+ else
ram_nsec(fuc, 14000);
- }
if (ram->base.type == NVKM_RAM_TYPE_DDR3) {
ram_wr32(fuc, 0x100264, 0x1);
--
2.10.0
2017 Apr 10
0
[PATCH 08/11] nvkm/ramgt215: Add train ptrn upload for GDDR5
...FP_KERNEL)))
+ return -ENOMEM;
+
+ for (i = 0; i < 0x100; i++) {
+ ret = gt215_ram_train_type(ram, i, ramcfg, train);
+ if (ret && ret != -ENOENT)
+ break;
+ }
+
+ switch (ram->type) {
+ case NVKM_RAM_TYPE_GDDR5:
+ ret = gt215_ram_train_upload_gddr5(ram, train);
+ break;
+ case NVKM_RAM_TYPE_DDR3:
+ ret = gt215_ram_train_upload_ddr3(ram, train);
+ break;
+ default:
+ ret = 0;
+ break;
+ }
+
+ kfree(train);
+ return ret;
+}
+
static void
-gt215_link_train_fini(struct gt215_ram *ram)
+gt215_ram_train_fini(struct nvkm_ram *ram)
{
- if (ram->ltrain.mem)
- ram->base.func->put(&am...
2017 Apr 10
11
Preparations for Fermi DRAM clock changes
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern upload routines from GK104+ now shared with GT215+
- Timing calculation for Fermi
- GDDR5 MR calculation from VBIOS timing table v1.0. Also useful for that
pesky GT 240.
- A routine to translate a VBIOS init
2017 Apr 10
14
RESEND Preparations for Fermi DRAM clock changes
Two patches went missing as a result of PEBCAK. No v2 marks as nothing
changed really. Just resending for easier enforcement of patch order
in other people's trees. Sorry for the noise.
Original message:
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern