search for: nvkm_ram

...dev/fb/ram.h index b60068b..ce8a98e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h @@ -1,6 +1,7 @@ #ifndef __NVKM_FB_RAM_PRIV_H__ #define __NVKM_FB_RAM_PRIV_H__ #include "priv.h" +#include <subdev/bios/M0209.h> int nvkm_ram_ctor(const struct nvkm_ram_func *, struct nvkm_fb *, enum nvkm_ram_type, u64 size, u32 tags, @@ -24,6 +25,22 @@ int gf100_ram_ctor(const struct nvkm_ram_func *, struct nvkm_fb *, int gf100_ram_get(struct nvkm_ram *, u64, u32, u32, u32, struct nvkm_mem **); void gf100_ram_put(struct nvkm_r...

No, no, these will not implement Fermi reclocking. This set of patches contains some of the preparatory work that I deem stable enough to move upstream. Notable changes - Training pattern upload routines from GK104+ now shared with GT215+ - Timing calculation for Fermi - GDDR5 MR calculation from VBIOS timing table v1.0. Also useful for that pesky GT 240. - A routine to translate a VBIOS init

.../drm/nouveau/nvkm/subdev/fb/ramgt215.c @@ -75,7 +75,7 @@ struct gt215_ramfuc { struct ramfuc_reg r_gpio[4]; }; -struct gt215_ltrain { +struct gt215_ram_train_ddr3 { enum { NVA3_TRAIN_UNKNOWN, NVA3_TRAIN_UNSUPPORTED, @@ -92,11 +92,11 @@ struct gt215_ltrain { struct gt215_ram { struct nvkm_ram base; struct gt215_ramfuc fuc; - struct gt215_ltrain ltrain; + struct gt215_ram_train_ddr3 ltrain; }; static void -gt215_link_train_calc(u32 *vals, struct gt215_ltrain *train) +gt215_link_train_calc(u32 *vals, struct gt215_ram_train_ddr3 *train) { int i, lo, hi; u8 median[8], bins[4] = {...

Two patches went missing as a result of PEBCAK. No v2 marks as nothing changed really. Just resending for easier enforcement of patch order in other people's trees. Sorry for the noise. Original message: No, no, these will not implement Fermi reclocking. This set of patches contains some of the preparatory work that I deem stable enough to move upstream. Notable changes - Training pattern

In bulletpoints: - Add some support for G94 and G96 reclocking. Has been tested on literally two cards, which is hardly adequate as "full coverage". On the other hand, the changes were small enough to make me confident this might work for others as well. - Fix NV50 wait for VBLANK when no monitor is plugged in. - Voltage related inprovements for GT21x. - Slightly improve Keplers

...= &ram->base.fb->subdev; + struct nvkm_device *device = subdev->device; + u32 cur1, cur2, cur4; + + cur1 = nvkm_rd32(device, 0x10f294); + cur2 = nvkm_rd32(device, 0x10f298); + cur4 = nvkm_rd32(device, 0x10f2a0); + + /* XXX: (G)DDR3? */ + switch ((!T(CWL)) * ram->base.type) { + case NVKM_RAM_TYPE_GDDR5: + T(CWL) = (cur1 & 0x00000380) >> 7; + break; + } + + timing[0] = (T(RP) << 24 | T(RAS) << 17 | T(RFC) << 8 | T(RC)); + timing[1] = (cur1 & ~0x03ffc07f) | + (T(RCDWR) << 20) | + (T(RCDRD) << 14) | + (T(CWL) << 7) | +...

A quick look over the memory reclocking part inside the maxwell mmiotraces kind of reminded me of the kepler memory reclocking, it looks for most parts the same. I didn't do a deep inspection so treat this with great care, but it seems to work at least on those maxwell gpus this was tested on. It depends on the PMU fixes for the fuc5 though, otherwise the PMU might not work as expected and

...case 0x15: diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c index 2cc074d..22e1e0b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c @@ -39,14 +39,18 @@ nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts) int rq = ram->freq < 1000000; /* XXX */ xd = !ram->next->bios.ramcfg_DLLoff; + lf = ram->next->bios.ramcfg_LowFreq; + pd = ram->next->bios.ramcfg_WCKPin; + vh = ram->next->bios.ramcfg_Hf_VREF; + vo = ram->next->bios.ramcfg_VREFD_off;...

From: Markus Elfring <elfring at users.sourceforge.net> Date: Wed, 21 Sep 2016 09:09:09 +0200 A few update suggestions were taken into account from static source code analysis. Markus Elfring (5): Use kmalloc_array() in nvbios_iccsense_parse() Use kmalloc_array() in gt215_link_train() Delete unnecessary braces Adjust a kzalloc() call in gt215_ram_new() Add space after an

...t215_ltrain *train) } /* Find the best value for 0x1111e0 */ - for (i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) if (bins[i] > qty) { bin = i + 3; qty = bins[i]; } - } train->r_100720 = 0; for (i = 0; i < 8; i++) { @@ -729,9 +728,8 @@ gt215_ram_calc(struct nvkm_ram *base, u32 freq) ram_mask(fuc, 0x1007e0, 0x22222222, r100760); } - if (device->chipset == 0xa3 && freq > 500000) { + if (device->chipset == 0xa3 && freq > 500000) ram_mask(fuc, 0x100700, 0x00000006, 0x00000000); - } /* Final switch */ if (mclk.pll) { @@ -...

Hello, Attached a small patch that correctly identifies the DLLoff bit for >=GF100. Marked RFC because I haven't seen any GDDR5 samples that *enable* the DLL. I'd like to verify whether the DLL should be reset when enabled. Could increase likelihood of succesfull reclock. Ben: could you do some experiments with this bit to see if GDDR5 needs some DLL reset logic? Thanks, and happy

...) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c index 0a0e44b..017a91d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c @@ -39,7 +39,7 @@ mcp77_ram_init(struct nvkm_ram *base) u32 flush = ((ram->base.size - (ram->poller_base + 0x40)) >> 5) - 1; /* Enable NISO poller for various clients and set their associated - * read address, only for MCP77/78 and MCP79/7A. (fd#25701) + * read address, only for MCP77/78 and MCP79/7A. (fd#27501) */ nvkm_...

...-git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index eef09bf..62359c2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -620,6 +620,12 @@ gf100_ram_train_init(struct nvkm_ram *ram) static int gf100_ram_init(struct nvkm_ram *base) { + struct nvkm_subdev *subdev = &base->fb->subdev; + struct nvkm_device *device = subdev->device; + + /* XXX Why does the blob do this? */ + nvkm_mask(device, 0x137360, 0x00000002, 0x00000000); + /* XXX: Don't hook up yet...

...git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index 38a7e2b..eef09bf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -556,7 +556,7 @@ gf100_ram_train_init_0(struct nvkm_ram *ram, struct gt215_ram_train *train) struct nvkm_device *device = subdev->device; int i, j; - if ((train->mask & 0x03d3) != 0x03d3) { + if ((train->mask & 0x03c3) != 0x03c3) { nvkm_warn(subdev, "missing link training data\n"); return -EINVAL; } @@ -575,10 +5...

...iff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index 093223d..fffd01a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -133,21 +133,22 @@ gf100_ram_calc(struct nvkm_ram *base, u32 freq) struct nvkm_device *device = subdev->device; struct nvkm_clk *clk = device->clk; struct nvkm_bios *bios = device->bios; - struct nvbios_ramcfg cfg; - u8 ver, cnt, len, strap; - struct { - u32 data; - u8 size; - } rammap, ramcfg, timing; + struct nvkm_ram_data *ne...

...-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c index 60ece0a8a2e1..1d2d6bae73cd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c @@ -87,7 +87,7 @@ nvkm_gddr3_calc(struct nvkm_ram *ram) WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; /* XXX: Get these values from the VBIOS instead */ DLL = !(ram->mr[1] & 0x1); - RON = !(ram->mr[1] & 0x300) >> 8; + RON = !((ram->mr[1] & 0x300) >> 8); break; default: ret...

...rivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c index e1d11f7..8d759f8a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c @@ -70,7 +70,7 @@ ramgddr3_wr_lo[] = { int nvkm_gddr3_calc(struct nvkm_ram *ram) { - int CL, WR, CWL, DLL = 0, ODT = 0, hi; + int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; switch (ram->next->bios.timing_ver) { case 0x10: @@ -79,6 +79,7 @@ nvkm_gddr3_calc(struct nvkm_ram *ram) WR = ram->next->bios.timing_10_WR; DLL = !ram->next->bios.ramcfg_DL...

...b/drm/nouveau/nvkm/subdev/clk/base.c index 1ca25dd..bfc6a49 100644 --- a/drm/nouveau/nvkm/subdev/clk/base.c +++ b/drm/nouveau/nvkm/subdev/clk/base.c @@ -274,11 +274,14 @@ static int nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) { struct nvkm_subdev *subdev = &clk->subdev; - struct nvkm_ram *ram = subdev->device->fb->ram; + struct nvkm_fb *fb = subdev->device->fb; struct nvkm_pci *pci = subdev->device->pci; struct nvkm_pstate *pstate; int ret, idx = 0; + if (pstatei == -1) + return 0; + list_for_each_entry(pstate, &clk->states, head) { if (idx...

I've splitted my big series between the part which actually fixes the engine reclocking bits and the part handling voltage/clock updates on temperature change, so that the more reviewed parts can be merged in faster. This series fixes a lot of Engine reclocking issues found on Fermi, Kepler and all Maxwell generation GPUs. It does _not_ fix memory reclocking on Fermi. It mostly contains of

Adds reclocking for NVA0, and a whole lot of work for other cards. Had these patches collecting dust for a little, but tested them with both my NVA0, and Martin's a while back. Success not guaranteed, but should be quite a leap forward. Happy reviewing and testing. Cheers, Roy