search for: nvkm_ppwr_chipset

this series makes use of the load counters we can use to get information about the current load of the gpu. This series includes the needed pmu bits and a debugfs interface to read them out. Currently the values are between 0 and 255, because it is much easier to implement it this way on the pmu. Karol Herbst (4): subdev/pmu/fuc: add gk104 pmu/fuc: add macros for pdaemon pwr counters

...ecv) * PERF data segment *****************************************************************************/ #ifdef INCLUDE_DATA +perf_attr_start: +// parameters +perf_polling_period_us: .b32 100000 + +// engine usage percentage +perf_eng_gr: .b8 0 +perf_eng_vdec: .b8 0 +perf_eng_mc: .b8 0 +#if NVKM_PPWR_CHIPSET >= GF100 +perf_eng_pcie: .b8 0 +#endif +.align 4 #endif /****************************************************************************** @@ -46,6 +58,78 @@ process(PROC_PERF, #perf_init, #perf_recv) // $r11 - data1 // $r0 - zero perf_recv: + push $r1 + + imm32($r10, PROC_HOST) + cmp b32 $...

these are usually used for dynamic reclocking on gt215 and newer The counters are used to get the load of the core, memory, video and pcie loads currently I expose the loads through a debugfs "current_load" file, but I want to move that to nvif and just add a wrapper around that in debugfs for convenience. Using nvif would have the advantage, that userspace tools can easily get loads

these are usually used for dynamic reclocking on gt215 and newer The counters are used to get the load of the core, memory, video and pcie loads currently I expose the loads through a debugfs "current_load" file, but I want to move that to nvif and just add a wrapper around that in debugfs for convenience Anyway there are still some issues I would like to discuss: 1. currently the

...ev/pmu/fuc/memx.fuc b/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc > index ec03f9a4..1663bf94 100644 > --- a/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc > +++ b/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc > @@ -82,15 +82,15 @@ memx_train_tail: > // $r0 - zero > memx_func_enter: > #if NVKM_PPWR_CHIPSET == GT215 > - movw $r8 0x1610 > + mov $r8 0x1610 > nv_rd32($r7, $r8) > imm32($r6, 0xfffffffc) > and $r7 $r6 > - movw $r6 0x2 > + mov $r6 0x2 > or $r7 $r6 > nv_wr32($r8, $r7) > #else > - movw $r6 0...

...diff --git a/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc b/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc index ec03f9a4..1663bf94 100644 --- a/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc +++ b/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc @@ -82,15 +82,15 @@ memx_train_tail: // $r0 - zero memx_func_enter: #if NVKM_PPWR_CHIPSET == GT215 - movw $r8 0x1610 + mov $r8 0x1610 nv_rd32($r7, $r8) imm32($r6, 0xfffffffc) and $r7 $r6 - movw $r6 0x2 + mov $r6 0x2 or $r7 $r6 nv_wr32($r8, $r7) #else - movw $r6 0x001620 + mov $r6 0x001620 imm32($r7, ~0x00000aa2); nv_rd32($r8, $r6) and $r8 $r7 @@ -101,7 +101,7 @@ memx_fu...

...PCOPY0_IDLE 0x00080000 +#define NV_PPWR_COUNTER_SIG_PCOPY1_IDLE 0x00100000 +#define NV_PPWR_COUNTER_SIG_PCOPY2_IDLE 0x00200000 +#define NV_PPWR_COUNTER_SIG_PCIE 0x20000000 #if NVKM_PPWR_CHIPSET < GK208 #define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x05d0) #endif -- 2.6.2

..._NEVER 0 +#define NV_PPWR_COUNTER_MODE_IF_ALL 1 +#define NV_PPWR_COUNTER_MODE_IF_ANY 2 +#define NV_PPWR_COUNTER_MODE_ALWAYS 3 #if NVKM_PPWR_CHIPSET < GK208 #define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x05d0) #endif -- 2.13.0

reworked this series quite a lot. Now we want the Host to configure the counters through the PMU. The series isn't complete though because it needs: 1. reordering 2. better commit messages but I felt like sending those out before doing a final version. I also found some weird register overwriting issue on the PMU I have to track down, because it interfers with the counter read out. I am

Patch 1 and 2 implement wait-for-vblank, required to remove flicker when reclocking memory Patch 3 and 4 allow me to do things between waiting for VBLANK and disabling FB, like pause PFIFO and wait for the engines to idle. This minimises the time PFIFO is paused, thus maximises performance. The rest of the patches speak for themselves. As the actual memory reclocking script is still somewhat prone

I think I am done reworking the series and getting to a point where I think it is basically finished. The configuration of the slots could be improved later on when working on dynamic reclocking, but for now it's good enough to report the current GPU utilization to userspace. Patches 1-4 imeplement PMU commands to setup and readout the counters. Patches 5-6 lets Nouveau make use of 1-4. Patch

...m/nouveau/nvkm/subdev/pmu/fuc/macros.fuc b/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc index 96fc984..0d5cbeb 100644 --- a/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc +++ b/drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc @@ -169,7 +169,7 @@ */ .b32 0 /* */ .skip 64 -#if NV_PPWR_CHIPSET < GK208 +#if NVKM_PPWR_CHIPSET < GK208 #define imm32(reg,val) /* */ movw reg ((val) & 0x0000ffff) /* */ sethi reg ((val) & 0xffff0000) -- 2.7.2

...diff --git a/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc b/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc index ec03f9a4..1663bf94 100644 --- a/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc +++ b/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc @@ -82,15 +82,15 @@ memx_train_tail: // $r0 - zero memx_func_enter: #if NVKM_PPWR_CHIPSET == GT215 - movw $r8 0x1610 + mov $r8 0x1610 nv_rd32($r7, $r8) imm32($r6, 0xfffffffc) and $r7 $r6 - movw $r6 0x2 + mov $r6 0x2 or $r7 $r6 nv_wr32($r8, $r7) #else - movw $r6 0x001620 + mov $r6 0x001620 imm32($r7, ~0x00000aa2); nv_rd32($r8, $r6) and $r8 $r7 @@ -101,7 +101,7 @@ memx_fu...

...diff --git a/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc b/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc index ec03f9a4..1663bf94 100644 --- a/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc +++ b/drm/nouveau/nvkm/subdev/pmu/fuc/memx.fuc @@ -82,15 +82,15 @@ memx_train_tail: // $r0 - zero memx_func_enter: #if NVKM_PPWR_CHIPSET == GT215 - movw $r8 0x1610 + mov $r8 0x1610 nv_rd32($r7, $r8) imm32($r6, 0xfffffffc) and $r7 $r6 - movw $r6 0x2 + mov $r6 0x2 or $r7 $r6 nv_wr32($r8, $r7) #else - movw $r6 0x001620 + mov $r6 0x001620 imm32($r7, ~0x00000aa2); nv_rd32($r8, $r6) and $r8 $r7 @@ -101,7 +101,7 @@ memx_fu...

...HE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#define NVKM_PPWR_CHIPSET GK104 +#define HW_TICKS_PER_US 324 + +//#define NVKM_FALCON_PC24 +#define NVKM_FALCON_UNSHIFTED_IO +//#define NVKM_FALCON_MMIO_UAS +//#define NVKM_FALCON_MMIO_TRAP + +#include "macros.fuc" + +.section #gk104_pmu_data +#define INCLUDE_PROC +#include "kernel.fuc" +#include "a...

....skip 0x0100 +memx_train_tail: #endif /****************************************************************************** @@ -260,6 +265,101 @@ memx_func_delay: // description // // $r15 - current (memx) +// $r4 - packet length +// $r3 - opcode desciption +// $r0 - zero +memx_func_train: +#if NVKM_PPWR_CHIPSET == GT215 +// $r5 - outer loop counter +// $r6 - inner loop counter +// $r7 - entry counter (#memx_train_head + $r7) + movw $r5 0x3 + movw $r7 0x0 + +// Read random memory to wake up... things + imm32($r9, 0x700000) + nv_rd32($r8,$r9) + movw $r14 0x2710 + call(nsec) + + memx_func_train_loop_outer:...

Re-use the therm-exported fan structure with only two minor modifications: - pwm_freq: u16 -> u32; - add fan_type (toggle or PWM) v2: - Do not memset the table to 0 as it erases the pre-set default values Signed-off-by: Martin Peres <martin.peres at free.fr> --- drm/Kbuild | 1 + drm/core/include/subdev/bios/fan.h | 1 + drm/core/subdev/bios/fan.c | 1

while trying out my pmu_counter patches on a gk208 gpu, I notived that the pmu is pretty much screwed up there. Karol Herbst (4): pmu/fuc: fix imm32 for gk208+ pmu/fuc: replace mov+sethi with imm32 pmu/fuc: call# seems to be broken on gk208 pmu/fuc: movw is somewhat weird on gk208, use mov instead drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h | 1598 +++++++++++------------

Following a series of patches that implement memory reclocking for NVA3/5/8 with DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics cards, but I expect reclocking now to work on many more. Testers can pick up these patches and test it by enabling pstate (nouveau.pstate=1). They should then be able to change clocks by writing to /sys/class/drm/card0/device/pstate. Correct

this series fixes the PMU on falcons v5 which fixes memory recklocking on kepler2 and would also allow us to enable memory recklocking on maxwell Karol Herbst (4): pmu/fuc: fix imm32 for gk208+ pmu/fuc: replace mov+sethi with imm32 pmu/fuc: use the call macro instead of using the call instruction directly pmu/fuc: use imm32 in ld/st macros