search for: nvkm_pmu_pgob

https://bugs.freedesktop.org/show_bug.cgi?id=92870 Bug ID: 92870 Summary: GF117M nvkm_pmu_pgob fault Product: xorg Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Driver/nouveau Assignee: nouveau at lists.freedesktop.org...

...f252fa2d7cf9 100644 > --- a/drm/nouveau/nvkm/engine/gr/gf100.c > +++ b/drm/nouveau/nvkm/engine/gr/gf100.c > @@ -1499,7 +1499,8 @@ gf100_gr_oneinit(struct nvkm_gr *base) > struct nvkm_device *device = gr->base.engine.subdev.device; > int ret, i, j; > > - nvkm_pmu_pgob(device->pmu, false); > + if (device->pmu) > + nvkm_pmu_pgob(device->pmu, false); I'd probably just change the condition in nvkm_pmu_pgob() to (pmu && pmu->func->pgob) ? > > ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000...

...engine/gr/gf100.c >>> +++ b/drm/nouveau/nvkm/engine/gr/gf100.c >>> @@ -1499,7 +1499,8 @@ gf100_gr_oneinit(struct nvkm_gr *base) >>> struct nvkm_device *device = gr->base.engine.subdev.device; >>> int ret, i, j; >>> >>> - nvkm_pmu_pgob(device->pmu, false); >>> + if (device->pmu) >>> + nvkm_pmu_pgob(device->pmu, false); >> I'd probably just change the condition in nvkm_pmu_pgob() to (pmu && >> pmu->func->pgob) ? > > It seems logical to me that the c...

Two trivial PMU-related fixes for Tegra: - Add a dummy func member to GK20A, since nvkm_pmmu_pgob() unconditionally dereferences it - Check whether a PMU actually exists before calling nvkm_pmmu_pgob(). During early bringup we are likely to not have a PMU Alexandre Courbot (2): pmu/gk20a: add dummy func gr/gf100: do not assume a PMU is present drm/nouveau/nvkm/engine/gr/gf100.c | 3 ++-

...184704463de09f0f310ac Author: Alexandre Courbot <acourbot at nvidia.com> Date: Thu Sep 3 17:39:52 2015 +0900 drm/nouveau/pmu: do not assume a PMU is present Some devices may not have a PMU. Avoid a NULL pointer dereference in such cases by checking whether the pointer given to nvkm_pmu_pgob() is valid. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> Signed-off-by: Ben Skeggs <bskeggs at redhat.com> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c index 27a79c0..d95eb86 100644 --- a/drivers/...

...>engine.subdev; + struct nvkm_device *device = subdev->device; u32 ret; + /* did you try turning it off and on again? Apparently we need this + * on pascal, otherwise secboot will just fail. + */ + nvkm_mask(device, 0x200, 0x1000, 0x0000); + nvkm_mask(device, 0x200, 0x1000, 0x1000); + nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); ret = nvkm_falcon_get(gr->fecs, subdev); -- 2.14.3

...e guard it against exectution on maxwell > Maybe, maybe not? I think it is fairly safe, but I kind of hoped somebody with more knowledge about these kind of things would respond and tells us this has to be done or maybe not. > > Greetings, > > Tobias > > > >> nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); >> ret = nvkm_falcon_get(gr->fecs, subdev);

...} recv; > }; > > +struct nvkm_pmu_load_data { > + u8 core; > + u8 mem; > + u8 video; > + u8 pcie; > +}; > + > int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process, > u32 message, u32 data0, u32 data1); > void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable); > @@ -48,4 +55,7 @@ void nvkm_memx_train(struct nvkm_memx *); > int nvkm_memx_train_result(struct nvkm_pmu *, u32 *, int); > void nvkm_memx_block(struct nvkm_memx *); > void nvkm_memx_unblock(struct nvkm_memx *); > + > +/* interface to PERF pro...

...t will just fail." > + */ > + nvkm_mask(device, 0x200, 0x1000, 0x0000); > + nvkm_mask(device, 0x200, 0x1000, 0x1000); > + It is needed with pascal, but does it harm other generations calling this init? Maybe guard it against exectution on maxwell Greetings, Tobias > nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); > > ret = nvkm_falcon_get(gr->fecs, subdev);

...ubdev/pmu.h +++ b/drm/nouveau/include/nvkm/subdev/pmu.h @@ -23,6 +23,13 @@ struct nvkm_pmu { } recv; }; +struct nvkm_pmu_load_data { + u8 core; + u8 mem; + u8 video; + u8 pcie; +}; + int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process, u32 message, u32 data0, u32 data1); void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable); @@ -48,4 +55,7 @@ void nvkm_memx_train(struct nvkm_memx *); int nvkm_memx_train_result(struct nvkm_pmu *, u32 *, int); void nvkm_memx_block(struct nvkm_memx *); void nvkm_memx_unblock(struct nvkm_memx *); + +/* interface to PERF process running on PMU */ +int nv...

...ubdev/pmu.h +++ b/drm/nouveau/include/nvkm/subdev/pmu.h @@ -23,6 +23,13 @@ struct nvkm_pmu { } recv; }; +struct nvkm_pmu_load_data { + u8 core; + u8 mem; + u8 video; + u8 pcie; +}; + int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process, u32 message, u32 data0, u32 data1); void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable); @@ -48,4 +55,7 @@ void nvkm_memx_train(struct nvkm_memx *); int nvkm_memx_train_result(struct nvkm_pmu *, u32 *, int); void nvkm_memx_block(struct nvkm_memx *); void nvkm_memx_unblock(struct nvkm_memx *); + +/* interface to PERF process running on PMU */ +int nv...

...ubdev/pmu.h +++ b/drm/nouveau/include/nvkm/subdev/pmu.h @@ -23,6 +23,13 @@ struct nvkm_pmu { } recv; }; +struct nvkm_pmu_load_data { + u8 core; + u8 mem; + u8 video; + u8 pcie; +}; + int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process, u32 message, u32 data0, u32 data1); void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable); @@ -48,4 +55,7 @@ void nvkm_memx_train(struct nvkm_memx *); int nvkm_memx_train_result(struct nvkm_pmu *, u32 *, int); void nvkm_memx_block(struct nvkm_memx *); void nvkm_memx_unblock(struct nvkm_memx *); + +/* interface to PERF process running on PMU */ +int nv...

Both patches should make the communicating with the PMU more stable. Karol Herbst (2): pmu: fix queued messages while getting no IRQ pmu: be more strict about locking drm/nouveau/nvkm/subdev/pmu/base.c | 49 ++++++++++++++++++++++++++++++++------ 1 file changed, 42 insertions(+), 7 deletions(-) -- 2.7.2

...d *)object; - struct gk20a_pmu_priv *priv = (void *)pmu; + struct gk20a_pmu_priv *priv = (void *)object; + struct nvkm_mc *pmc = nvkm_mc(object); int ret; - ret = nvkm_subdev_init(&pmu->base); + ret = nvkm_subdev_init(&priv->base.base); if (ret) return ret; - pmu->pgob = nvkm_pmu_pgob; + priv->pmu_state = PMU_STATE_STARTING; + ret = gk20a_init_pmu_setup_hw1(priv, pmc); + if (ret) + return ret; + + nv_wr32(priv, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001); + nv_wr32(priv, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002); + nv_wr32(priv, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003); -...

...sion: %d\n", + pmu->desc->app_version); + ret = -EINVAL; + goto err; + } + + ret = gk20a_init_pmu_setup_sw(ppmu); if (ret) - return ret; + goto err; + + pmu->pmu_state = PMU_STATE_STARTING; + ret = gk20a_init_pmu_setup_hw1(ppmu, pmc); + if (ret) + goto err; - pmu->pgob = nvkm_pmu_pgob; + ret = nvkm_subdev_init(&ppmu->base); + if (ret) + goto err; - /* init pwr perf counter */ - nv_wr32(pmu, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001); - nv_wr32(pmu, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002); - nv_wr32(pmu, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003); + ppmu->pgob = nv...

...len, align); + if (!len) + return -EINVAL; + + down_write(&allocator->rw_sema); + bitmap_clear(allocator->bitmap, addr - allocator->base, len); + up_write(&allocator->rw_sema); + + allocator_dbg(allocator, "[out] addr %d, len %d", addr, len); + + return 0; +} + void nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable) { diff --git a/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drm/nouveau/nvkm/subdev/pmu/gk20a.c index a49934bbe637..0fd2530301a3 100644 --- a/drm/nouveau/nvkm/subdev/pmu/gk20a.c +++ b/drm/nouveau/nvkm/subdev/pmu/gk20a.c @@ -20,21 +20,67 @@ * DEALINGS IN THE SOFTWARE....

...ct nvkm_mc *pmc = nvkm_mc(object); >> int ret; >> >> - ret = nvkm_subdev_init(&pmu->base); >> + ret = nvkm_subdev_init(&priv->base.base); >> if (ret) >> return ret; >> >> - pmu->pgob = nvkm_pmu_pgob; >> + priv->pmu_state = PMU_STATE_STARTING; >> + ret = gk20a_init_pmu_setup_hw1(priv, pmc); >> + if (ret) >> + return ret; >> + >> + nv_wr32(priv, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001); >> + nv_wr32(priv,...

...>rw_sema); > + bitmap_clear(allocator->bitmap, addr - allocator->base, len); > + up_write(&allocator->rw_sema); > + > + allocator_dbg(allocator, "[out] addr %d, len %d", addr, len); > + > + return 0; > +} > + > void > nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable) > { > diff --git a/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drm/nouveau/nvkm/subdev/pmu/gk20a.c > index a49934bbe637..0fd2530301a3 100644 > --- a/drm/nouveau/nvkm/subdev/pmu/gk20a.c > +++ b/drm/nouveau/nvkm/subdev/pmu/gk20a.c > @@ -20,21 +20,67 @@...

...>rw_sema); > + bitmap_clear(allocator->bitmap, addr - allocator->base, len); > + up_write(&allocator->rw_sema); > + > + allocator_dbg(allocator, "[out] addr %d, len %d", addr, len); > + > + return 0; > +} > + > void > nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable) > { > diff --git a/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drm/nouveau/nvkm/subdev/pmu/gk20a.c > index a49934bbe637..0fd2530301a3 100644 > --- a/drm/nouveau/nvkm/subdev/pmu/gk20a.c > +++ b/drm/nouveau/nvkm/subdev/pmu/gk20a.c > @@ -20,21 +20,67 @@...

this series makes use of the load counters we can use to get information about the current load of the gpu. This series includes the needed pmu bits and a debugfs interface to read them out. Currently the values are between 0 and 255, because it is much easier to implement it this way on the pmu. Karol Herbst (4): subdev/pmu/fuc: add gk104 pmu/fuc: add macros for pdaemon pwr counters