search for: nvkm_pmu

...ate mode 100644 drm/nouveau/nvkm/subdev/pmu/gk20a.h diff --git a/drm/nouveau/include/nvkm/subdev/pmu.h b/drm/nouveau/include/nvkm/subdev/pmu.h index 7b86acc634a0..659b4e0ba02b 100644 --- a/drm/nouveau/include/nvkm/subdev/pmu.h +++ b/drm/nouveau/include/nvkm/subdev/pmu.h @@ -1,7 +1,20 @@ #ifndef __NVKM_PMU_H__ #define __NVKM_PMU_H__ #include <core/subdev.h> +#include <core/device.h> +#include <subdev/mmu.h> +#include <linux/debugfs.h> +struct pmu_buf_desc { + struct nvkm_gpuobj *pmubufobj; + struct nvkm_vma pmubufvma; + size_t size; +}; +struct pmu_priv_vm { + struct nvkm_...

...ubdev/pmu/gk20a.h > > diff --git a/drm/nouveau/include/nvkm/subdev/pmu.h b/drm/nouveau/include/nvkm/subdev/pmu.h > index 7b86acc634a0..659b4e0ba02b 100644 > --- a/drm/nouveau/include/nvkm/subdev/pmu.h > +++ b/drm/nouveau/include/nvkm/subdev/pmu.h > @@ -1,7 +1,20 @@ > #ifndef __NVKM_PMU_H__ > #define __NVKM_PMU_H__ > #include <core/subdev.h> > +#include <core/device.h> > +#include <subdev/mmu.h> > +#include <linux/debugfs.h> > > +struct pmu_buf_desc { > + struct nvkm_gpuobj *pmubufobj; > + struct nvkm_vma pmubufvma;...

...ubdev/pmu/gk20a.h > > diff --git a/drm/nouveau/include/nvkm/subdev/pmu.h b/drm/nouveau/include/nvkm/subdev/pmu.h > index 7b86acc634a0..659b4e0ba02b 100644 > --- a/drm/nouveau/include/nvkm/subdev/pmu.h > +++ b/drm/nouveau/include/nvkm/subdev/pmu.h > @@ -1,7 +1,20 @@ > #ifndef __NVKM_PMU_H__ > #define __NVKM_PMU_H__ > #include <core/subdev.h> > +#include <core/device.h> > +#include <subdev/mmu.h> > +#include <linux/debugfs.h> > > +struct pmu_buf_desc { > + struct nvkm_gpuobj *pmubufobj; > + struct nvkm_vma pmubufvma;...

Add a PMU constructor so implementations that extend the nvkm_pmu structure can have all base members properly initialized. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/subdev/pmu/base.c | 21 +++++++++++++++------ drm/nouveau/nvkm/subdev/pmu/priv.h | 2 ++ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/...

...t; > #include <engine/fifo.h> > diff --git a/drm/nouveau/include/nvkm/subdev/pmu.h b/drm/nouveau/include/nvkm/subdev/pmu.h > index e61923d..be3c60e 100644 > --- a/drm/nouveau/include/nvkm/subdev/pmu.h > +++ b/drm/nouveau/include/nvkm/subdev/pmu.h > @@ -23,6 +23,13 @@ struct nvkm_pmu { > } recv; > }; > > +struct nvkm_pmu_load_data { > + u8 core; > + u8 mem; > + u8 video; > + u8 pcie; > +}; > + > int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process, > u32 message, u32 data0, u32 dat...

...0A_PMU_DMAIDX_PHYS_VID = 2, + GK20A_PMU_DMAIDX_PHYS_SYS_COH = 3, + GK20A_PMU_DMAIDX_PHYS_SYS_NCOH = 4, + GK20A_PMU_DMAIDX_RSVD = 5, + GK20A_PMU_DMAIDX_PELPG = 6, + GK20A_PMU_DMAIDX_END = 7 +}; + +struct pmu_buf_desc { + struct nvkm_gpuobj *obj; + struct nvkm_vma vma; + size_t size; +}; + +struct nvkm_pmu_priv_vm { + struct nvkm_gpuobj *mem; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; +}; + +/* Choices for pmu_state */ +enum { + PMU_STATE_OFF, /*0 PMU is off */ + PMU_STATE_STARTING, /*1 PMU is on, but not booted */ + PMU_STATE_INIT_RECEIVED /*2 PMU init message received...

...#include <core/device.h> #include <engine/fifo.h> diff --git a/drm/nouveau/include/nvkm/subdev/pmu.h b/drm/nouveau/include/nvkm/subdev/pmu.h index e61923d..be3c60e 100644 --- a/drm/nouveau/include/nvkm/subdev/pmu.h +++ b/drm/nouveau/include/nvkm/subdev/pmu.h @@ -23,6 +23,13 @@ struct nvkm_pmu { } recv; }; +struct nvkm_pmu_load_data { + u8 core; + u8 mem; + u8 video; + u8 pcie; +}; + int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process, u32 message, u32 data0, u32 data1); void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable); @@ -48,4 +55,7 @@ void nvkm_memx_train(stru...

...#include <core/device.h> #include <engine/fifo.h> diff --git a/drm/nouveau/include/nvkm/subdev/pmu.h b/drm/nouveau/include/nvkm/subdev/pmu.h index e61923d..be3c60e 100644 --- a/drm/nouveau/include/nvkm/subdev/pmu.h +++ b/drm/nouveau/include/nvkm/subdev/pmu.h @@ -23,6 +23,13 @@ struct nvkm_pmu { } recv; }; +struct nvkm_pmu_load_data { + u8 core; + u8 mem; + u8 video; + u8 pcie; +}; + int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process, u32 message, u32 data0, u32 data1); void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable); @@ -48,4 +55,7 @@ void nvkm_memx_train(stru...

...#include <core/device.h> #include <engine/fifo.h> diff --git a/drm/nouveau/include/nvkm/subdev/pmu.h b/drm/nouveau/include/nvkm/subdev/pmu.h index e61923d..be3c60e 100644 --- a/drm/nouveau/include/nvkm/subdev/pmu.h +++ b/drm/nouveau/include/nvkm/subdev/pmu.h @@ -23,6 +23,13 @@ struct nvkm_pmu { } recv; }; +struct nvkm_pmu_load_data { + u8 core; + u8 mem; + u8 video; + u8 pcie; +}; + int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process, u32 message, u32 data0, u32 data1); void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable); @@ -48,4 +55,7 @@ void nvkm_memx_train(stru...

Both patches should make the communicating with the PMU more stable. Karol Herbst (2): pmu: fix queued messages while getting no IRQ pmu: be more strict about locking drm/nouveau/nvkm/subdev/pmu/base.c | 49 ++++++++++++++++++++++++++++++++------ 1 file changed, 42 insertions(+), 7 deletions(-) -- 2.7.2

...0A_PMU_DMAIDX_PHYS_VID = 2, + GK20A_PMU_DMAIDX_PHYS_SYS_COH = 3, + GK20A_PMU_DMAIDX_PHYS_SYS_NCOH = 4, + GK20A_PMU_DMAIDX_RSVD = 5, + GK20A_PMU_DMAIDX_PELPG = 6, + GK20A_PMU_DMAIDX_END = 7 +}; + +struct pmu_buf_desc { + struct nvkm_gpuobj *obj; + struct nvkm_vma vma; + size_t size; +}; + +struct nvkm_pmu_priv_vm { + struct nvkm_gpuobj *mem; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; +}; + +/*Choices for pmu_state*/ +enum { + PMU_STATE_OFF, /*0 PMU is off */ + PMU_STATE_STARTING, /*1 PMU is on, but not booted */ + PMU_STATE_INIT_RECEIVED /*2 PMU init message received *...

I encountered while stresstesting the reclocking code, that rarely (1 out of 20.000+ requests) we don't get any IRQ in nvkm_pmu_intr. This means we have a queued message on the pmu, but nouveau doesn't read it and waits infinitely in nvkm_pmu_send: if (reply) { wait_event(pmu->recv.wait, (pmu->recv.process == 0)); therefore let us use wait_event_timeout with a 1s timeout frame and just check whether there is...

I encountered while stresstesting the reclocking code, that rarely (1 out of 20.000+ requests) we don't get any IRQ in nvkm_pmu_intr. This means we have a queued message on the pmu, but nouveau doesn't read it and waits infinitely in nvkm_pmu_send: if (reply) { wait_event(pmu->recv.wait, (pmu->recv.process == 0)); therefore let us use wait_event_timeout with a 1s timeout frame and just check whether there is...

...pmu/gt215.c b/drm/nouveau/nvkm/subdev/pmu/gt215.c index 8ba7fa4ca75b..dcf9eaf274aa 100644 --- a/drm/nouveau/nvkm/subdev/pmu/gt215.c +++ b/drm/nouveau/nvkm/subdev/pmu/gt215.c @@ -24,17 +24,8 @@ #include "priv.h" #include "fuc/gt215.fuc3.h" -static void -gt215_pmu_reset(struct nvkm_pmu *pmu) -{ - struct nvkm_device *device = pmu->subdev.device; - nvkm_mask(device, 0x022210, 0x00000001, 0x00000000); - nvkm_mask(device, 0x022210, 0x00000001, 0x00000001); -} - static const struct nvkm_pmu_func gt215_pmu = { - .reset = gt215_pmu_reset, .code.data = gt215_pmu_code, .code.size...

reworked this series quite a lot. Now we want the Host to configure the counters through the PMU. The series isn't complete though because it needs: 1. reordering 2. better commit messages but I felt like sending those out before doing a final version. I also found some weird register overwriting issue on the PMU I have to track down, because it interfers with the counter read out. I am

...cons instances into their owning subdev * rework gk20a's PMU implementation and add dummy gm20b PMU driver Alexandre Courbot (15): core: constify nv*_printk macros mc: add nvkm_mc_enabled() function core: add falcon library functions pmu: instanciate the falcon in PMU device pmu: add nvkm_pmu_ctor() function pmu/gk20a: use nvkm_pmu_ctor() pmu/gk20a: simplify code a bit pmu/gk20a: use falcon library functions gm20b: add dummy PMU device secboot: fix functions definitions secboot: use falcon library gr: add fini() hook gr/gf100: split gf100_gr_init_ctxctl() gr/gf100: ins...

...dev/pmu/base.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/pmu/base.c b/drm/nouveau/nvkm/subdev/pmu/base.c index 81a5583..eb248fd 100644 --- a/drm/nouveau/nvkm/subdev/pmu/base.c +++ b/drm/nouveau/nvkm/subdev/pmu/base.c @@ -100,9 +100,16 @@ nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], } /* acquire data segment access */ - do { + nvkm_wr32(device, 0x10a580, 0x00000001); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x10a580) == 0x00000001) + break; nvkm_wr32(device, 0x10a580, 0x00000001); - } while (nvkm_rd32(device, 0x...

I think I am done reworking the series and getting to a point where I think it is basically finished. The configuration of the slots could be improved later on when working on dynamic reclocking, but for now it's good enough to report the current GPU utilization to userspace. Patches 1-4 imeplement PMU commands to setup and readout the counters. Patches 5-6 lets Nouveau make use of 1-4. Patch

...GK20A_PMU_DMAIDX_PELPG = 6, >> + GK20A_PMU_DMAIDX_END = 7 >> +}; >> + >> +struct pmu_buf_desc { >> + struct nvkm_gpuobj *obj; >> + struct nvkm_vma vma; >> + size_t size; >> +}; >> + >> +struct nvkm_pmu_priv_vm { >> + struct nvkm_gpuobj *mem; >> + struct nvkm_gpuobj *pgd; >> + struct nvkm_vm *vm; >> +}; >> + >> +/*Choices for pmu_state*/ >> +enum { >> + PMU_STATE_OFF, /*0 PMU is off */ >> + PMU_STATE_S...

...m/subdev/secboot/acr_r352.c @@ -924,6 +924,19 @@ acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb) } } + /* reset the PMU if needed */ + if (acr->base.boot_falcon == NVKM_SECBOOT_FALCON_PMU && + !nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_PMU)) { + struct nvkm_pmu *pmu = subdev->device->pmu; + if (pmu) { + ret = nvkm_subdev_init(&pmu->subdev); + if (ret < 0) { + nvkm_error(subdev, "Failed to reset PMU\n"); + return ret; + } + } + } + return 0; } -- 2.13.2