search for: nvkm_msec

.../subdev/pmu/base.c index 81a5583..eb248fd 100644 --- a/drm/nouveau/nvkm/subdev/pmu/base.c +++ b/drm/nouveau/nvkm/subdev/pmu/base.c @@ -100,9 +100,16 @@ nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], } /* acquire data segment access */ - do { + nvkm_wr32(device, 0x10a580, 0x00000001); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x10a580) == 0x00000001) + break; nvkm_wr32(device, 0x10a580, 0x00000001); - } while (nvkm_rd32(device, 0x10a580) != 0x00000001); + ) < 0) { + if (reply) + mutex_unlock(&subdev->mutex); + return -EBUSY; + } /* write the packet */ nvkm_...

.../subdev/pmu/base.c index fafbe2a..398b6a8 100644 --- a/drm/nouveau/nvkm/subdev/pmu/base.c +++ b/drm/nouveau/nvkm/subdev/pmu/base.c @@ -106,9 +106,15 @@ nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], } /* acquire data segment access */ - do { + nvkm_wr32(device, 0x10a580, 0x00000001); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x10a580) == 0x00000001) + break; nvkm_wr32(device, 0x10a580, 0x00000001); - } while (nvkm_rd32(device, 0x10a580) != 0x00000001); + ) < 0) { + mutex_unlock(&subdev->mutex); + return -EBUSY; + } /* write the packet */ nvkm_wr32(device, 0x...

...bdev/pmu/base.c > > +++ b/drm/nouveau/nvkm/subdev/pmu/base.c > > @@ -100,9 +100,16 @@ nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], > > } > > > > /* acquire data segment access */ > > - do { > > + nvkm_wr32(device, 0x10a580, 0x00000001); > > + if (nvkm_msec(device, 2000, > > + if (nvkm_rd32(device, 0x10a580) == 0x00000001) > > + break; > > nvkm_wr32(device, 0x10a580, 0x00000001); > > - } while (nvkm_rd32(device, 0x10a580) != 0x00000001); > > + ) < 0) { > > + if (reply) > > + mutex_unlock(&amp;subdev-&gt...

...drm/nouveau/nvkm/subdev/clk/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -366,11 +366,20 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx) if (info->coef) { nvkm_wr32(device, addr + 0x04, info->coef); nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); - nvkm_msec(device, 2000, + + /* Test PLL lock */ + nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000); + if (nvkm_msec(device, 2000, if (nvkm_rd32(device, addr + 0x00) & 0x00020000) break; - ); - nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004); + ) < 0) { + nvkm_war...

Following a series of three patches, two of which have been sitting in my tree for a while, the third is the result of some inspection of an NV134 BIOS that seems to use the 0xaf upcode to upload training patterns. Please test! Roy Ps. Sorry they come from yet another e-mail address. My previous provider, eclipso, actively blocks users of git send-email. Inquiries fall on deaf ears, hence I

Corresponds with GT215. Don't rely on the lock test logic being unconditionally enabled, and disable test logic when done (presumably to save power). v2: Remove warning, nvkm_msec already warns on time-out Signed-off-by: Roy Spliet <nouveau at spliet.org> --- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c | 8 +++++++- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c | 8 +++++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau...

...00000000); @@ -376,12 +377,14 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx) nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); /* Test PLL lock */ + bypass_state = nvkm_rd32(device, addr + 0x00) & 0x00000010; nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000); nvkm_msec(device, 2000, if (nvkm_rd32(device, addr + 0x00) & 0x00020000) break; ); - nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010); + if (bypass_state) + nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010); /* Enable sync mode */ nvkm_mask(device, addr + 0x00,...

...c_intr(struct nvkm_ltc *ltc) > } > } > > +void > +gf100_ltc_invalidate(struct nvkm_ltc *ltc) > +{ > + struct nvkm_device *device = ltc->subdev.device; > + s64 taken; > + > + nvkm_wr32(device, 0x70004, 0x00000001); > + if ((taken = nvkm_msec(device, 2000, I don't suppose you have access to information on more realistic timeouts? I'd like to improve all the potential 2s timeout values across the driver in general, to avoid things hanging for a long time when the GPU craps itself :) > + if ((nvkm_rd32(device, 0...

...veau/nvkm/subdev/clk/gf100.c @@ -375,14 +375,6 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx) nvkm_wr32(device, addr + 0x04, info->coef); nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); - /* Test PLL lock */ - nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000); - nvkm_msec(device, 2000, - if (nvkm_rd32(device, addr + 0x00) & 0x00020000) - break; - ); - nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010); - /* Enable sync mode */ nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004); } diff --git a/drm/nouveau/nvkm/subdev/clk/gk104.c b/dr...

...er.h> > + > static int > gk104_pcie_version_supported(struct nvkm_pci *pci) > { > @@ -142,6 +144,11 @@ gk104_pcie_set_link_speed(struct nvkm_pci *pci, enum nvkm_pcie_speed speed) > break; > } > > + /* wait for ltssm idle */ > + nvkm_msec(device, 200, > + if ((nvkm_rd32(device, 0x8c040) & 0x1f) == 0) > + break; > + ); What if it doesn't idle? Should you still do the below things? > nvkm_mask(device, 0x8c040, 0xc0000, mask_value); > nvkm_mask(device, 0...

Due to the lack of implicit synchronization between CPU and GPU on Tegra systems (like what PCI provides for dGPUs), the instmem implementation of GK20A/GM20B relied on the slow, legacy PRAMIN so that CPU accesses used the same path as GPU, making sure we see the same data on both ends. The recent Nouveau refactoring introduced acquire/release functions on instmem that help us understand the

...77,13 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx) nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); /* Test PLL lock */ - nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000); + bypass_state = nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000) & 0x00000010; nvkm_msec(device, 2000, if (nvkm_rd32(device, addr + 0x00) & 0x00020000) break; ); - nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010); + if (bypass_state) + nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010); /* Enable sync mode */ nvkm_mask(device, addr + 0x00,...

...bump into this obscenity: > >>> > >>> int > >>> gm200_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *falcon) > >>> { > >>> nvkm_falcon_mask(falcon, 0x040, 0x00000000, 0x00000000); > >>> > >>> if (nvkm_msec(falcon->owner->device, 10, > >>> if (!(nvkm_falcon_rd32(falcon, 0x10c) & 0x00000006)) > >>> break; > >>> ) < 0) > >>> return -ETIMEDOUT; > >>> > >>>...

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

...;> +void >>> +gf100_ltc_invalidate(struct nvkm_ltc *ltc) >>> +{ >>> + struct nvkm_device *device = ltc->subdev.device; >>> + s64 taken; >>> + >>> + nvkm_wr32(device, 0x70004, 0x00000001); >>> + if ((taken = nvkm_msec(device, 2000, >> I don't suppose you have access to information on more realistic >> timeouts? I'd like to improve all the potential 2s timeout values >> across the driver in general, to avoid things hanging for a long time >> when the GPU craps itself :) > >...

...t; int > >>>>>> gm200_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *falcon) > >>>>>> { > >>>>>> nvkm_falcon_mask(falcon, 0x040, 0x00000000, 0x00000000); > >>>>>> > >>>>>> if (nvkm_msec(falcon->owner->device, 10, > >>>>>> if (!(nvkm_falcon_rd32(falcon, 0x10c) & 0x00000006)) > >>>>>> break; > >>>>>> ) < 0) > >>>>>> return -...

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

...39;d love to but a quick glance at the code caused me to bump into this obscenity: > > > > int > > gm200_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *falcon) > > { > > nvkm_falcon_mask(falcon, 0x040, 0x00000000, 0x00000000); > > > > if (nvkm_msec(falcon->owner->device, 10, > > if (!(nvkm_falcon_rd32(falcon, 0x10c) & 0x00000006)) > > break; > > ) < 0) > > return -ETIMEDOUT; > > > > return 0; > > } > > > >...

Attached patch fixes an issue reported by Pierre Moreau, that prevents reclocking of GT21x and MCP7x from working after "the big rewrite". Please review and push forward for kernel 4.3. Thanks! Roy

...44 --- a/drm/nouveau/nvkm/subdev/ltc/gm107.c +++ b/drm/nouveau/nvkm/subdev/ltc/gm107.c @@ -43,10 +43,8 @@ gm107_ltc_cbc_wait(struct nvkm_ltc *ltc) for (c = 0; c < ltc->ltc_nr; c++) { for (s = 0; s < ltc->lts_nr; s++) { const u32 addr = 0x14046c + (c * 0x2000) + (s * 0x200); - nvkm_msec(device, 2000, - if (!nvkm_rd32(device, addr)) - break; - ); + nvkm_wait_msec(device, 2000, addr, + 0x00000004, 0x00000000); } } } -- 2.7.0