Displaying 10 results from an estimated 10 matches for "nvkm_memory_addr".
2016 Mar 01
1
[PATCH 1/2] fifo/gf100: take runlist target into account
...evice = subdev->device;
struct nvkm_memory *cur;
int nr = 0;
+ int target;
mutex_lock(&subdev->mutex);
cur = fifo->runlist.mem[fifo->runlist.active];
@@ -67,7 +68,10 @@ gf100_fifo_runlist_commit(struct gf100_fifo *fifo)
}
nvkm_done(cur);
- nvkm_wr32(device, 0x002270, nvkm_memory_addr(cur) >> 12);
+ target = (nvkm_memory_target(cur) == NVKM_MEM_TARGET_HOST) ? 0x3 : 0x0;
+
+ nvkm_wr32(device, 0x002270, (nvkm_memory_addr(cur) >> 12) |
+ (target << 28));
nvkm_wr32(device, 0x002274, 0x01f00000 | nr);
if (wait_event_timeout(fifo->runlist.wait,
--
2....
2016 Oct 27
0
[PATCH 2/3] fb/gk20a: use regular gf100's functions
...ed documentation files (the "Software"),
@@ -22,21 +22,14 @@
#include "priv.h"
#include "gf100.h"
-#include <core/memory.h>
-
-static void
-gk20a_fb_init(struct nvkm_fb *fb)
-{
- struct nvkm_device *device = fb->subdev.device;
- nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(fb->mmu_wr) >> 8);
- nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(fb->mmu_rd) >> 8);
-}
-
+/* GK20A's FB is similar to GF100's, but without the ability to allocate VRAM */
static const struct nvkm_fb_func
gk20a_fb = {
+ .dtor = gf100_fb_dtor,
.oneinit = gf100_fb_oneini...
2016 Oct 27
5
[PATCH 0/3] fb fixes for gk20a/gm20b
After observing random crashes on Tegra devices when patch "fb/gf100: defer DMA
mapping of scratch page to oneinit() hook" was applied, I noticed that moving
the 100c10 page allocation to the oneinit() hook resulted in that page being
now allocated for Tegra as well, and accesses be made to members of gf100_fb
which were not accessible because gk20a_fb_new() called nvkm_fb_new_()
2017 Apr 27
0
[PATCH] drm/nouveau/fifo/gk104-: Silence a locking warning
.../nvkm/engine/fifo/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
@@ -148,7 +148,7 @@ gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl)
case NVKM_MEM_TARGET_NCOH: target = 3; break;
default:
WARN_ON(1);
- return;
+ goto unlock;
}
nvkm_wr32(device, 0x002270, (nvkm_memory_addr(mem) >> 12) |
@@ -160,6 +160,7 @@ gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl)
& 0x00100000),
msecs_to_jiffies(2000)) == 0)
nvkm_error(subdev, "runlist %d update timeout\n", runl);
+unlock:
mutex_unlock(&subdev->mutex);
}
2019 Sep 17
0
[PATCH 0/2] drm/nouveau: Two more fixes
...accept a system memory address instead.
I guess this would be the right thing to do here in that situation.
The more obvious (from a "reading the code" POV) thing to do would be
to write Tegra-specific versions of the functions that use
nvkm_memory_bar2() to perform this mapping, and use nvkm_memory_addr()
instead but I'm not sure if we need/want to go to that effort. It's
conceivable it could be required at some point.
Ben.
>
> It'd be great to get Lyude's feedback on the second patch, since that
> call to pci_disable_device() was rather oddly placed and I'm not sur...
2019 Sep 16
6
[PATCH 0/2] drm/nouveau: Two more fixes
From: Thierry Reding <treding at nvidia.com>
Hi Ben,
I messed up the ordering of patches in my tree a bit, so these two fixes
got separated from the others. I don't consider these particularily
urgent because the crash that the first one fixes only happens on gp10b
which we don't enable by default yet and the second patch fixes a crash
that only happens on module unload (or driver
2019 Sep 16
9
[PATCH 0/6] drm/nouveau: Preparatory work for GV11B support
From: Thierry Reding <treding at nvidia.com>
Hi Ben,
these are a couple of patches that are in preparation for adding GV11B
support. The fundamental issue that these are trying to solve is that
the GV11B is the first Tegra incarnation of the GPU where the aperture
really matters. All prior generations would accept any of them.
For dGPUs we usually allocate memory in VRAM, so the default
2019 Nov 02
13
[PATCH v2 0/9] drm/nouveau: Various fixes for GP10B
From: Thierry Reding <treding at nvidia.com>
Hi Ben,
here's a revised subset of the patches I had sent out a couple of weeks
ago. I've reworked the BAR2 accesses in the way that you had suggested,
which at least for GP10B turned out to be fairly trivial to do. I have
not looked in detail at this for GV11B yet, but a cursory look showed
that BAR2 is accessed in more places, so the
2019 Dec 09
11
[PATCH v3 0/9] drm/nouveau: Various fixes for GP10B
From: Thierry Reding <treding at nvidia.com>
Hi Ben,
here's a revised subset of the patches I had sent out a couple of weeks
ago. I've reworked the BAR2 accesses in the way that you had suggested,
which at least for GP10B turned out to be fairly trivial to do. I have
not looked in detail at this for GV11B yet, but a cursory look showed
that BAR2 is accessed in more places, so the
2016 Jan 18
8
[PATCH 0/5] nouveau: unified firmware loading functions
This patchset centralizes the firmware-loading procedure to one set of functions
instead of having each engine load its firmware as it pleases. This helps ensure
that all firmware comes from the same place, namely nvidia/<chip>/.
This changes where the firmware is fetched from for falcon/xtensa/bios, but
these locations never seemed to have been official anyway. Also for most (all?)
chips