search for: nvkm_mask

.../subdev/clk/gf100.c @@ -368,6 +368,7 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx) struct gf100_clk_info *info = &clk->eng[idx]; struct nvkm_device *device = clk->base.subdev.device; const u32 addr = 0x137000 + (idx * 0x20); + bool bypass_state = false; if (idx <= 7) { nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000); nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000); @@ -376,12 +377,14 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx) nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); /* Test PLL lock */ + bypass_state = nvkm_rd32(device,...

...ing this BYPASS_PLL_CHECK is on 0x10: lookup -ac0 0x137000 0x10 PCLOCK.CLK0_CTRL => { BYPASS_PLL_CHECK | UNK12 = 0 } Also, disabling this bit on other CLKs doesn't seem to break anything. v2: add back PLL lock test v3: add restoring original value after PLL lock test v4: read the bit with nvkm_mask Signed-off-by: Mark Menzynski <mmenzyns at redhat.com> --- drm/nouveau/nvkm/subdev/clk/gf100.c | 8 +++++--- drm/nouveau/nvkm/subdev/clk/gk104.c | 6 ++++-- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/clk/gf100.c b/drm/nouveau/nvkm/subdev/clk/gf100...

This is an initial implementation of HDMI 3D mode support for the nouveau kernel driver. It works on all of the hardware that I have available to test at the moment, but I am unsure as to the overall approach taken for setting HDMI InfoFrames, there's no support for g84 or gf119 disps, and the criteria for enabling stereo support for an output seems a bit iffy. The first four patches arrange

....c +++ b/drm/nouveau/nvkm/subdev/ibus/gf100.c @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ -#include <subdev/ibus.h> +#include "priv.h" static void gf100_ibus_intr_hub(struct nvkm_subdev *ibus, int i) @@ -56,7 +56,7 @@ gf100_ibus_intr_gpc(struct nvkm_subdev *ibus, int i) nvkm_mask(device, 0x128128 + (i * 0x0400), 0x00000200, 0x00000000); } -static void +void gf100_ibus_intr(struct nvkm_subdev *ibus) { struct nvkm_device *device = ibus->device; @@ -92,8 +92,21 @@ gf100_ibus_intr(struct nvkm_subdev *ibus) } } +static int +gf100_ibus_init(struct nvkm_subdev *ibus...

.../nvkm/subdev/secboot/base.c index b718ba79177c..05c62549c39b 100644 --- a/drm/nouveau/nvkm/subdev/secboot/base.c +++ b/drm/nouveau/nvkm/subdev/secboot/base.c @@ -85,8 +85,8 @@ nvkm_secboot_falcon_enable(struct nvkm_secboot *sb) /* enable IRQs */ nvkm_wr32(device, sb->base + 0x010, 0xff); - nvkm_mask(device, 0x640, sb->irq_mask, 0x1000000); - nvkm_mask(device, 0x644, sb->irq_mask, 0x1000000); + nvkm_mask(device, 0x640, sb->irq_mask, sb->irq_mask); + nvkm_mask(device, 0x644, sb->irq_mask, sb->irq_mask); return 0; } -- 2.7.2

...clk/gf100.c index 78c449b..f9a4918 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -366,11 +366,20 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx) if (info->coef) { nvkm_wr32(device, addr + 0x04, info->coef); nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); - nvkm_msec(device, 2000, + + /* Test PLL lock */ + nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000); + if (nvkm_msec(device, 2000, if (nvkm_rd32(device, addr + 0x00) & 0x00020000) break; - ); - nvkm_mask(device, addr +...

...clk/gf100.c index 78c449b..026baff 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -366,11 +366,17 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx) if (info->coef) { nvkm_wr32(device, addr + 0x04, info->coef); nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); + + /* Test PLL lock */ + nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000); nvkm_msec(device, 2000, if (nvkm_rd32(device, addr + 0x00) & 0x00020000) break; ); - nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004); +...

...m/subdev/clk/gf100.c b/drm/nouveau/nvkm/subdev/clk/gf100.c index 7f67f9f5..7ba2a000 100644 --- a/drm/nouveau/nvkm/subdev/clk/gf100.c +++ b/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -375,14 +375,6 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx) nvkm_wr32(device, addr + 0x04, info->coef); nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); - /* Test PLL lock */ - nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000); - nvkm_msec(device, 2000, - if (nvkm_rd32(device, addr + 0x00) & 0x00020000) - break; - ); - nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010); -...

Following a series of three patches, two of which have been sitting in my tree for a while, the third is the result of some inspection of an NV134 BIOS that seems to use the 0xaf upcode to upload training patterns. Please test! Roy Ps. Sorry they come from yet another e-mail address. My previous provider, eclipso, actively blocks users of git send-email. Inquiries fall on deaf ears, hence I

.../nouveau/nvkm/subdev/clk/gf100.c index 7f67f9f5..fe56817b 100644 --- a/drm/nouveau/nvkm/subdev/clk/gf100.c +++ b/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -381,7 +381,6 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx) if (nvkm_rd32(device, addr + 0x00) & 0x00020000) break; ); - nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010); /* Enable sync mode */ nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004); diff --git a/drm/nouveau/nvkm/subdev/clk/gk104.c b/drm/nouveau/nvkm/subdev/clk/gk104.c index 0b37e3da..22cac304 100644 --- a/drm/nouveau/nvkm/subdev/clk/gk104.c +++...

This series adds support for GM20B PLL's Maxwell features, namely glitchless switch and (more importantly) DFS support. DFS lets the PLL lower its output speed according to input current variations, making the clock more stable and allowing it to run safely at lower voltage. All GM20B additions are done in the last patch, which consequently ends up being considerably big ; fortunately, it

...n, bool en) 53 { 54 struct nvkm_device *device = chan->disp->base.engine.subdev.device; 55 const u64 mask = 0x00000001 << chan->chid.user; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 56 if (!en) { 57 nvkm_mask(device, 0x610090, mask, 0x00000000); 58 nvkm_mask(device, 0x6100a0, mask, 0x00000000); 59 } else { 60 nvkm_mask(device, 0x6100a0, mask, mask); 61 } 62 } regards, dan carpenter

...t;v0.flags & + NV50_DISP_MTHD_V1_SOR_HDMI_PWR_FLAG_VENDOR_INFOFRAME) { + vendor_infoframe = data; + if ((ret = nvif_unpack(-ENOSYS, &data, &size, + *vendor_infoframe, 0, 0, true))) + return ret; + } + + if (size) + return -E2BIG; + if (!(ctrl & 0x40000000)) { nvkm_mask(device, 0x6165a4 + hoff, 0x40000000, 0x00000000); nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf119.c index 632f02d..c492cd7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/...

...@@ -52,7 +52,7 @@ void gf119_disp_chan_intr(struct nv50_disp_chan *chan, bool en) { struct nvkm_device *device = chan->disp->base.engine.subdev.device; - const u64 mask = 0x00000001 << chan->chid.user; + const u64 mask = 0x00000001ULL << chan->chid.user; if (!en) { nvkm_mask(device, 0x610090, mask, 0x00000000); nvkm_mask(device, 0x6100a0, mask, 0x00000000); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c index 57719f675eec..43ae3b092e43 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv...

...base) { struct gf100_gr *gr = gf100_gr(base); struct nvkm_subdev *subdev = &base->engine.subdev; + struct nvkm_device *device = subdev->device; u32 ret; + /* did you try turning it off and on again? Apparently we need this + * on pascal, otherwise secboot will just fail. + */ + nvkm_mask(device, 0x200, 0x1000, 0x0000); + nvkm_mask(device, 0x200, 0x1000, 0x1000); + nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); ret = nvkm_falcon_get(gr->fecs, subdev); -- 2.14.3

...94233d0119df..52a234b1ef01 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c @@ -906,7 +906,9 @@ static void gk104_grctx_generate_r419f78(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; - nvkm_mask(device, 0x419f78, 0x00000001, 0x00000000); + + /* bit 3 set disables loads in fp helper invocations, we need it enabled */ + nvkm_mask(device, 0x419f78, 0x00000009, 0x00000000); } void diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk1...

...g) return; - if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) { + mask = 0, data = 0; + if (ram->diff.rammap_11_0a_03fe) { data |= cfg->bios.rammap_11_0a_03fe << 12; mask |= 0x001ff000; } @@ -1178,31 +1179,36 @@ gk104_ram_prog_0(struct gk104_ram *ram, u32 freq) } nvkm_mask(device, 0x10f468, mask, data); - if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) { + mask = 0, data = 0; + if (ram->diff.rammap_11_0a_0400) { data |= cfg->bios.rammap_11_0a_0400; mask |= 0x00000001; } nvkm_mask(device, 0x10f420, mask, data); - if (mask = 0, data = 0, ram...

...b/drm/nouveau/nvkm/engine/gr/ctxgk20a.c index ddaa16a..ad0a6cf 100644 --- a/drm/nouveau/nvkm/engine/gr/ctxgk20a.c +++ b/drm/nouveau/nvkm/engine/gr/ctxgk20a.c @@ -55,7 +55,7 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gk104_grctx_generate_rop_active_fbps(gr); - nvkm_mask(device, 0x5044b0, 0x8000000, 0x8000000); + nvkm_mask(device, 0x5044b0, 0x08000000, 0x08000000); gf100_gr_wait_idle(gr); diff --git a/drm/nouveau/nvkm/subdev/fb/ramgk104.c b/drm/nouveau/nvkm/subdev/fb/ramgk104.c index 0d20563..2614365 100644 --- a/drm/nouveau/nvkm/subdev/fb/ramgk104.c +++ b/dr...

...t; This should probably be a negative error code instead of "ret"? 54 } 55 56 switch (info.type) { 57 case PLL_VPLL0: 58 case PLL_VPLL1: 59 nvkm_wr32(device, info.reg + 0, 0x10000611); 60 nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1); 61 nvkm_mask(device, info.reg + 8, 0x7fff00ff, (P << 28) | 62 (M2 << 16) | N2); 63 break; 64 case PLL_MEMORY...

...> } > > + /* wait for ltssm idle */ > + nvkm_msec(device, 200, > + if ((nvkm_rd32(device, 0x8c040) & 0x1f) == 0) > + break; > + ); What if it doesn't idle? Should you still do the below things? > nvkm_mask(device, 0x8c040, 0xc0000, mask_value); > nvkm_mask(device, 0x8c040, 0x1, 0x1); > } > -- > 2.21.0 > > _______________________________________________ > Nouveau mailing list > Nouveau at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/nouveau