search for: nvkm_info

...lds[] = { "fanboost", "downclock", "critical", "shutdown" }; int temperature = therm->func->temp_get(therm); @@ -94,10 +94,10 @@ nvkm_therm_sensor_event(struct nvkm_therm *therm, enum nvkm_therm_thrs thrs, if (dir == NVKM_THERM_THRS_FALLING) nvkm_info(subdev, "temperature (%i C) went below the '%s' threshold\n", - temperature, thresolds[thrs]); + temperature, thresholds[thrs]); else nvkm_info(subdev, "temperature (%i C) hit the '%s' threshold\n", - temperature, thresolds[thrs]); + te...

...sb->irq_mask = 0x1000000; > + sb->enable_mask = 0x2000; > + break; > + default: > + nvdev_error(device, "invalid secure boot falcon\n"); > + return -EINVAL; > + }; > + > + nvkm_info(&sb->subdev, "securely managed falcons:\n"); > + for_each_set_bit(fid, &sb->func->managed_falcons, > + NVKM_SECBOOT_FALCON_END) > + nvkm_info(&sb->subdev, "- %s\n", managed_falcons_names[fid]); > + &g...

...> + nvkm_error(&clk->subdev, "couldn't parse base clock\n"); > + else if (nvbios_baseclock_get_entry(bios, &header, header.boost_entry, &boost_entry)) > + nvkm_error(&clk->subdev, "couldn't parse boost clock\n"); > + else > + nvkm_info(&clk->subdev, "base: %i MHz, boost: %i MHz\n", > + base_entry.clock_mhz / 2, boost_entry.clock_mhz / 2); This is probably just me missing some elementary electronic knowledge about clocks, but why do you divide the clock frequency by two? Regards, Pierre > + } > + &g...

...0x1000000; >> + sb->enable_mask = 0x2000; >> + break; >> + default: >> + nvdev_error(device, "invalid secure boot falcon\n"); >> + return -EINVAL; >> + }; >> + >> + nvkm_info(&sb->subdev, "securely managed falcons:\n"); >> + for_each_set_bit(fid, &sb->func->managed_falcons, >> + NVKM_SECBOOT_FALCON_END) >> + nvkm_info(&sb->subdev, "- %s\n", managed_falcons_names[fid]...

...n; const char *mode; + struct nvbios_baseclk_header h; + + nvkm_subdev_ctor(&nvkm_clk, device, index, 0, subdev); + + if (bios && !nvbios_baseclock_parse(bios, &h)) { + struct nvbios_baseclk_entry base, boost; + if (!nvbios_baseclock_entry(bios, &h, h.boost, &boost)) + nvkm_info(subdev, "boost: %i MHz\n", + boost.clock_mhz / 2); + if (!nvbios_baseclock_entry(bios, &h, h.base, &base)) + nvkm_info(subdev, "base: %i MHz\n", + base.clock_mhz / 2); + } - nvkm_subdev_ctor(&nvkm_clk, device, index, 0, &clk->subdev); clk->...

...T, &node->handle, GFP_KERNEL, - &imem->attrs); + imem->attrs); if (!node->base.vaddr) { nvkm_error(subdev, "cannot allocate DMA memory\n"); return -ENOMEM; @@ -597,10 +597,9 @@ gk20a_instmem_new(struct nvkm_device *device, int index, nvkm_info(&imem->base.subdev, "using IOMMU\n"); } else { - init_dma_attrs(&imem->attrs); - dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); - dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); - dma_set_attr(DMA_ATTR_WRITE_COMBINE, &imem->attrs); + ime...

...T, &node->handle, GFP_KERNEL, - &imem->attrs); + imem->attrs); if (!node->base.vaddr) { nvkm_error(subdev, "cannot allocate DMA memory\n"); return -ENOMEM; @@ -597,10 +597,9 @@ gk20a_instmem_new(struct nvkm_device *device, int index, nvkm_info(&imem->base.subdev, "using IOMMU\n"); } else { - init_dma_attrs(&imem->attrs); - dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); - dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); - dma_set_attr(DMA_ATTR_WRITE_COMBINE, &imem->attrs); + ime...

...T, &node->handle, GFP_KERNEL, - &imem->attrs); + imem->attrs); if (!node->base.vaddr) { nvkm_error(subdev, "cannot allocate DMA memory\n"); return -ENOMEM; @@ -597,10 +597,9 @@ gk20a_instmem_new(struct nvkm_device *device, int index, nvkm_info(&imem->base.subdev, "using IOMMU\n"); } else { - init_dma_attrs(&imem->attrs); - dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); - dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); - dma_set_attr(DMA_ATTR_WRITE_COMBINE, &imem->attrs); + ime...

.../gf100.c index ae9ab5b..0ed56ff 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1805,6 +1805,7 @@ gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,      return ret;      if (gr->firmware) { +          nvkm_info(&gr->base.engine.subdev, "using external firmware\n");                if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) ||             gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) ||             gf100_gr_ctor_fw(gr, "gpccs_inst", &am...

...VG); if (bios && !nvbios_baseclock_parse(bios, &h)) { struct nvbios_baseclk_entry base, boost; - if (!nvbios_baseclock_entry(bios, &h, h.boost, &boost)) + if (!nvbios_baseclock_entry(bios, &h, h.boost, &boost)) { + clk->boost_khz = boost.clock_mhz * 1000; nvkm_info(subdev, "boost: %i MHz\n", boost.clock_mhz / 2); - if (!nvbios_baseclock_entry(bios, &h, h.base, &base)) + } + + if (!nvbios_baseclock_entry(bios, &h, h.base, &base)) { + clk->base_khz = base.clock_mhz * 1000; nvkm_info(subdev, "base: %i MHz\n"...

...amp; - pci->pdev->device == quirk->chip_device) { + (quirk->chip_vendor == (u16)PCI_ANY_ID || + pci->pdev->vendor == quirk->chip_vendor) && + (quirk->chip_device == (u16)PCI_ANY_ID || + pci->pdev->device == quirk->chip_device)) { nvkm_info(subdev, "forcing default agp mode to %dX, " "use NvAGP=<mode> to override\n", quirk->mode); -- Ondrej Zary

...amp; - pci->pdev->device == quirk->chip_device) { + (quirk->chip_vendor == (u16)PCI_ANY_ID || + pci->pdev->vendor == quirk->chip_vendor) && + (quirk->chip_device == (u16)PCI_ANY_ID || + pci->pdev->device == quirk->chip_device)) { nvkm_info(subdev, "forcing default agp mode to %dX, " "use NvAGP=<mode> to override\n", quirk->mode); -- Ondrej Zary

...0a_instmem_new(struct nvkm_device *device, int index, imem->mm = &tdev->iommu.mm; imem->domain = tdev->iommu.domain; imem->iommu_pgshift = tdev->iommu.pgshift; - imem->cpu_map = gk20a_instobj_cpu_map_iommu; imem->iommu_bit = tdev->func->iommu_bit; nvkm_info(&imem->base.subdev, "using IOMMU\n"); } else { init_dma_attrs(&imem->attrs); - /* We will access the memory through our own mapping */ dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); dma_se...

this series solves different issues we encounter on kepler cards while reclocking: 1. core clock doesn't change at all and produces a volting error (patch 1) this can happen when the voltage table has only 0ed values in the header so we have to parse the entries itself, which contain the right voltages 2. kepler won't clock to highest cstates (patch 2) this happens, because there are

...oost_entry, &boost_entry)) Same comment as above > nvkm_error(&clk->subdev, "couldn't parse boost clock\n"); > - else > + else { > + clk->base_clock = base_entry.clock_mhz * 1000; > + clk->boost_clock = boost_entry.clock_mhz * 1000; > nvkm_info(&clk->subdev, "base: %i MHz, boost: %i MHz\n", > base_entry.clock_mhz / 2, boost_entry.clock_mhz / 2); > + } > + } else { > + clk->boost_mode = -1; You only listed values 0, 1, 2 in the commit message, so what is -1 for? Disabling nvboost is already taken car...

...device, int index, > imem->mm = &tdev->iommu.mm; > imem->domain = tdev->iommu.domain; > imem->iommu_pgshift = tdev->iommu.pgshift; > - imem->cpu_map = gk20a_instobj_cpu_map_iommu; > imem->iommu_bit = tdev->func->iommu_bit; > > nvkm_info(&imem->base.subdev, "using IOMMU\n"); > } else { > init_dma_attrs(&imem->attrs); > - /* We will access the memory through our own mapping */ > dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); > dma_set_attr(DMA_ATTR_WEAK_ORDERING, &i...

This series fixes most of the issues regarding volting on GPUs with any form of GPU Boost inside their vbios, which is mainly Kepler and newer, but we find some boosting related tables in Fermi vbios' already In the end reclocking should work on most Kepler cards without any issues Karol Herbst (19): bios/volt: handle voltage table version 0x50 with 0ed header volt: properly detect entry

..._entry, &base_entry)) + nvkm_error(&clk->subdev, "couldn't parse base clock\n"); + else if (nvbios_baseclock_get_entry(bios, &header, header.boost_entry, &boost_entry)) + nvkm_error(&clk->subdev, "couldn't parse boost clock\n"); + else + nvkm_info(&clk->subdev, "base: %i MHz, boost: %i MHz\n", + base_entry.clock_mhz / 2, boost_entry.clock_mhz / 2); + } + clk->func = func; INIT_LIST_HEAD(&clk->states); clk->domains = func->domains; -- 2.6.3

...bdev, "couldn't parse base clock\n"); > > + else if (nvbios_baseclock_get_entry(bios, &amp;header, header.boost_entry, > > &amp;boost_entry)) > > + nvkm_error(&amp;clk->subdev, "couldn't parse boost clock\n"); > > + else > > + nvkm_info(&amp;clk->subdev, "base: %i MHz, boost: %i MHz\n", > > + base_entry.clock_mhz / 2, boost_entry.clock_mhz / 2); > > This is probably just me missing some elementary electronic knowledge about > clocks, but why do you divide the clock frequency by two? > This is b...

...ailed */ ret = nvkm_rd32(device, sb->base + 0x040); if (ret) { - nvkm_error(&sb->subdev, "ACR boot failed, ret 0x%08x", ret); + nvkm_error(subdev, "ACR boot failed, ret 0x%08x", ret); falcon_clear_halt_interrupt(device, sb->base); return -EINVAL; } + nvkm_info(subdev, "signed firmware successfully loaded\n"); + return 0; } -- 2.7.3