search for: nvkm_gpuobj_memcpy_to

...lob); @@ -421,7 +435,6 @@ acr_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs, struct ls_ucode_img_r352 *img = ls_ucode_img_r352(_img); const struct acr_r352_ls_func *ls_func = acr->func->ls_func[_img->falcon_id]; - u8 gdesc[ls_func->bl_desc_size]; nvkm_gpuobj_memcpy_to(wpr_blob, pos, &img->wpr_header, sizeof(img->wpr_header)); @@ -447,6 +460,8 @@ acr_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs, nvkm_done(wpr_blob); + kfree(gdesc); + return 0; } @@ -771,7 +786,11 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm...

...@ ls_ucode_mgr_write_wpr(struct acr_r352 *acr, struct ls_ucode_mgr *mgr, nvkm_kmap(wpr_blob); list_for_each_entry(img, &mgr->img_list, node) { + const struct acr_r352_ls_func *ls_func = + acr->func->ls_func[img->falcon_id]; + u8 gdesc[ls_func->bl_desc_size]; + nvkm_gpuobj_memcpy_to(wpr_blob, pos, &img->wpr_header, sizeof(img->wpr_header)); @@ -369,18 +366,10 @@ ls_ucode_mgr_write_wpr(struct acr_r352 *acr, struct ls_ucode_mgr *mgr, &img->lsb_header, sizeof(img->lsb_header)); /* Generate and write BL descriptor */ - if (!img->...

...acr->func->ls_func[_img->falcon_id]; > - u8 gdesc[ls_func->bl_desc_size]; > if there are no guarantees that (ls_func->bl_desc_size & 0x4 == 0), then we need to memset a bit more, because 4 bytes at the time are actually copied inside nvkm_gpuobj_memcpy_to later in that code, but the last 4 bytes are only partly memset to 0. If ls_func->bl_desc_size is always a multiple of 0x4, then it isn't as important, but still better to be fixed. Or maybe nvkm_gpuobj_memcpy_to should do that handling and check if the size is a multiple of 0x4 and otherwi...

...cr->func->ls_func[_img->falcon_id]; >> - u8 gdesc[ls_func->bl_desc_size]; >> > > if there are no guarantees that (ls_func->bl_desc_size & 0x4 == 0), > then we need to memset a bit more, because 4 bytes at the time are > actually copied inside nvkm_gpuobj_memcpy_to later in that code, but > the last 4 bytes are only partly memset to 0. I think this is unchanged from the original code, yes? The memset() is always against bl_desc_size; I haven't changed that. > If ls_func->bl_desc_size is always a multiple of 0x4, then it isn't as > import...

..._img->falcon_id]; >>> - u8 gdesc[ls_func->bl_desc_size]; >>> >> >> if there are no guarantees that (ls_func->bl_desc_size & 0x4 == 0), >> then we need to memset a bit more, because 4 bytes at the time are >> actually copied inside nvkm_gpuobj_memcpy_to later in that code, but >> the last 4 bytes are only partly memset to 0. > > I think this is unchanged from the original code, yes? The memset() is > always against bl_desc_size; I haven't changed that. > right, but I think before we would upload undefined data (because we ru...

...list_for_each_entry(_img, imgs, node) { + struct ls_ucode_img_r352 *img = ls_ucode_img_r352(_img); const struct acr_r352_ls_func *ls_func = - acr->func->ls_func[img->falcon_id]; + acr->func->ls_func[_img->falcon_id]; u8 gdesc[ls_func->bl_desc_size]; nvkm_gpuobj_memcpy_to(wpr_blob, pos, &img->wpr_header, @@ -335,14 +354,14 @@ ls_ucode_mgr_write_wpr(struct acr_r352 *acr, struct list_head *imgs, &img->lsb_header, sizeof(img->lsb_header)); /* Generate and write BL descriptor */ - ls_func->generate_bl_desc(&acr->base, img, wpr_...

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

...r - write the WPR blob contents + */ +static int +ls_ucode_mgr_write_wpr(struct gm200_secboot *gsb, struct ls_ucode_mgr *mgr, + struct nvkm_gpuobj *wpr_blob) +{ + struct ls_ucode_img *img; + u32 pos = 0; + + nvkm_kmap(wpr_blob); + + list_for_each_entry(img, &mgr->img_list, node) { + nvkm_gpuobj_memcpy_to(wpr_blob, pos, &img->wpr_header, + sizeof(img->wpr_header)); + + nvkm_gpuobj_memcpy_to(wpr_blob, img->wpr_header.lsb_offset, + &img->lsb_header, sizeof(img->lsb_header)); + + /* Generate and write BL descriptor */ + if (!img->ucode_header) { + u8 desc...

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

...mgr *mgr, u8 desc[gsb->func->bl_desc_size]; struct gm200_flcn_bl_desc gdesc; - ls_ucode_img_populate_bl_desc(img, gsb->wpr_addr, + ls_ucode_img_populate_bl_desc(img, gsb->acr_wpr_addr, &gdesc); gsb->func->fixup_bl_desc(&gdesc, &desc); nvkm_gpuobj_memcpy_to(wpr_blob, @@ -846,8 +846,11 @@ gm200_secboot_prepare_ls_blob(struct gm200_secboot *gsb) /* If WPR address and size are not fixed, set them to fit the LS blob */ if (!gsb->wpr_size) { - gsb->wpr_addr = gsb->ls_blob->addr; - gsb->wpr_size = gsb->ls_blob->size; + gsb->...

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

...nc)[img->falcon_id]; + u8 gdesc[ls_func->bl_desc_size]; + + ls_func->generate_bl_desc(img, gsb->acr_wpr_addr, + &gdesc); - ls_ucode_img_populate_bl_desc(img, gsb->acr_wpr_addr, - &gdesc); - gsb->func->fixup_bl_desc(&gdesc, &desc); nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.bl_data_off, - &desc, gsb->func->bl_desc_size); + &gdesc, ls_func->bl_desc_size); } /* Copy ucode */ @@ -815,11 +644,12 @@ gm200_secboot_prepare_ls_blob(struct gm200_secboot *gsb) ls_ucode_mgr_init(&mgr);...