Displaying 4 results from an estimated 4 matches for "nvkm_fifo_chan_inst_lock".
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nvkm_fifo_chan_inst_locked
2019 Sep 17
1
[PATCH 1/6] drm/nouveau: fault: Store aperture in fault information
...gine/fifo/gk104.c
> index 5d4b695cab8e..81cbe1cc4804 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
> @@ -519,9 +519,10 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info)
> chan = nvkm_fifo_chan_inst_locked(&fifo->base, info->inst);
>
> nvkm_error(subdev,
> - "fault %02x [%s] at %016llx engine %02x [%s] client %02x "
> + "fault %02x [%s] at %016llx aperture %02x engine %02x [%s] client %02x "
>...
2019 Sep 16
0
[PATCH 1/6] drm/nouveau: fault: Store aperture in fault information
...drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
index 5d4b695cab8e..81cbe1cc4804 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
@@ -519,9 +519,10 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info)
chan = nvkm_fifo_chan_inst_locked(&fifo->base, info->inst);
nvkm_error(subdev,
- "fault %02x [%s] at %016llx engine %02x [%s] client %02x "
+ "fault %02x [%s] at %016llx aperture %02x engine %02x [%s] client %02x "
"[%s%s] reason %02x [%s] on channel %d [%010llx %s]\n",...
2019 Sep 16
9
[PATCH 0/6] drm/nouveau: Preparatory work for GV11B support
From: Thierry Reding <treding at nvidia.com>
Hi Ben,
these are a couple of patches that are in preparation for adding GV11B
support. The fundamental issue that these are trying to solve is that
the GV11B is the first Tegra incarnation of the GPU where the aperture
really matters. All prior generations would accept any of them.
For dGPUs we usually allocate memory in VRAM, so the default
2020 Oct 30
6
[PATCH 0/5] Improve Robust Channel (RC) recovery for Turing
This is an initial series of patches to improve channel recovery on Turing GPUs
with the goal of improving reliability enough to eventually enable SVM for
Turing. It's likely follow up patches will be required to fully address problems
with less trivial workloads than what I have been able to test thus far.
This series primarily addresses a number of hardware changes to interrupt layout
and