search for: nvkm_fifo

...(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index 22443fe4a39f..8e36cdd0e5fb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -178,7 +178,12 @@ nvkm_fifo_info(struct nvkm_engine *engine, u64 mthd, u64 *data) return ret; switch (mthd) { - case NV_DEVICE_HOST_CHANNELS: *data = fifo->chid ? fifo->chid->nr : 0; return 0; + case NV_DEVICE_HOST_CHANNELS: + if (fifo->func->chid_total) + *data = fifo->func->chid_total(fifo); +...

This is an initial series of patches to improve channel recovery on Turing GPUs with the goal of improving reliability enough to eventually enable SVM for Turing. It's likely follow up patches will be required to fully address problems with less trivial workloads than what I have been able to test thus far. This series primarily addresses a number of hardware changes to interrupt layout and

...) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h index 4bd6e1e7c413..c0fb545efb2b 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h @@ -25,7 +25,12 @@ struct nvkm_fifo_chan { struct nvkm_gpuobj *inst; struct nvkm_gpuobj *push; struct nvkm_vmm *vmm; - void __iomem *user; + + union { + struct nvkm_memory *mem; + void __iomem *user; + }; + u64 addr; u32 size; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c b/drivers/gpu/drm/nouveau/nvkm/en...

Hi there, Resending these now that they've had some more polish and testing, and I heard that Ben's vacation is over :-) These patches work as a starting point for more explicit error mechanisms and better robustness. At the moment, when a job hangs or faults, it seems that nouveau doesn't quite know how to handle the situation and often results in a hang. Some of these situations

...rs/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -447,7 +447,7 @@ gf100_fifo_nonstall_allow(struct nvkm_event *event, int type, int index) spin_unlock_irqrestore(&fifo->lock, flags); } -void +static void gf100_fifo_nonstall_block(struct nvkm_event *event, int type, int index) { struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event); -- 2.27.0

.../nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c > index 5d4b695cab8e..81cbe1cc4804 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c > @@ -519,9 +519,10 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) > chan = nvkm_fifo_chan_inst_locked(&fifo->base, info->inst); > > nvkm_error(subdev, > - "fault %02x [%s] at %016llx engine %02x [%s] client %02x " > + "fault %02x [%s] at...

...) & 0x3ff, &node); > diff --git a/drm/nouveau/nv84_fence.c b/drm/nouveau/nv84_fence.c > index bf429ca..952bc48 100644 > --- a/drm/nouveau/nv84_fence.c > +++ b/drm/nouveau/nv84_fence.c > @@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm) > { > struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); > struct nv84_fence_priv *priv; > + u32 domain; > int ret; > > priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); > @@ -231,10 +232,12 @@ nv84_fence_create(struct nouveau_drm *drm) > priv-&gt...

...it a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 5d4b695cab8e..81cbe1cc4804 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -519,9 +519,10 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) chan = nvkm_fifo_chan_inst_locked(&fifo->base, info->inst); nvkm_error(subdev, - "fault %02x [%s] at %016llx engine %02x [%s] client %02x " + "fault %02x [%s] at %016llx aperture %02x engine %02x [%s] client %02x "...

...;& sw) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index 8c7ba32..47c1682 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -81,6 +81,7 @@ nv40_fifo_init(struct nvkm_fifo *base) case 0x49: case 0x4b: nvkm_wr32(device, 0x002230, 0x00000001); + /* fall through */ case 0x40: case 0x41: case 0x42: diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c index c306835..7112992 100644 --- a/drivers/gpu/dr...

...int idx, struct nvkm_engine **); - int (*cipher )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*disp )(struct nvkm_device *, int idx, struct nvkm_disp **); - int (*dma )(struct nvkm_device *, int idx, struct nvkm_dma **); - int (*fifo )(struct nvkm_device *, int idx, struct nvkm_fifo **); - int (*gr )(struct nvkm_device *, int idx, struct nvkm_gr **); - int (*ifb )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*me )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*mpeg )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*ms...

...int idx, struct nvkm_engine **); - int (*cipher )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*disp )(struct nvkm_device *, int idx, struct nvkm_disp **); - int (*dma )(struct nvkm_device *, int idx, struct nvkm_dma **); - int (*fifo )(struct nvkm_device *, int idx, struct nvkm_fifo **); - int (*gr )(struct nvkm_device *, int idx, struct nvkm_gr **); - int (*ifb )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*me )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*mpeg )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*ms...

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot:

...;& sw) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index 8c7ba32..47c1682 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -81,6 +81,7 @@ nv40_fifo_init(struct nvkm_fifo *base) case 0x49: case 0x4b: nvkm_wr32(device, 0x002230, 0x00000001); + /* fall through */ case 0x40: case 0x41: case 0x42: diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c index c306835..7112992 100644 --- a/drivers/gpu/dr...

...(nvbo->tile_flags >> 8) & 0x3ff, &node); diff --git a/drm/nouveau/nv84_fence.c b/drm/nouveau/nv84_fence.c index bf429cabbaa8..b981f85de888 100644 --- a/drm/nouveau/nv84_fence.c +++ b/drm/nouveau/nv84_fence.c @@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm) { struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); struct nv84_fence_priv *priv; + u32 domain; int ret; priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); @@ -231,10 +232,17 @@ nv84_fence_create(struct nouveau_drm *drm) priv->base.context_base = fence_context_alloc(priv->base.contexts...

...c, (nvbo->tile_flags >> 8) & 0x3ff, &node); diff --git a/drm/nouveau/nv84_fence.c b/drm/nouveau/nv84_fence.c index bf429ca..952bc48 100644 --- a/drm/nouveau/nv84_fence.c +++ b/drm/nouveau/nv84_fence.c @@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm) { struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); struct nv84_fence_priv *priv; + u32 domain; int ret; priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); @@ -231,10 +232,12 @@ nv84_fence_create(struct nouveau_drm *drm) priv->base.context_base = fence_context_alloc(priv->base.contexts...

...c, (nvbo->tile_flags >> 8) & 0x3ff, &node); diff --git a/drm/nouveau/nv84_fence.c b/drm/nouveau/nv84_fence.c index bf429ca..b981f85 100644 --- a/drm/nouveau/nv84_fence.c +++ b/drm/nouveau/nv84_fence.c @@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm) { struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); struct nv84_fence_priv *priv; + u32 domain; int ret; priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); @@ -231,10 +232,17 @@ nv84_fence_create(struct nouveau_drm *drm) priv->base.context_base = fence_context_alloc(priv->base.contexts...

...t a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c > index 8c7ba32..47c1682 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c > @@ -81,6 +81,7 @@ nv40_fifo_init(struct nvkm_fifo *base) > case 0x49: > case 0x4b: > nvkm_wr32(device, 0x002230, 0x00000001); > + /* fall through */ > case 0x40: > case 0x41: > case 0x42: > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c >...

...diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index 47c16821c37f..2d61fd832ddb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -81,7 +81,7 @@ nv40_fifo_init(struct nvkm_fifo *base) case 0x49: case 0x4b: nvkm_wr32(device, 0x002230, 0x00000001); - /* fall through */ + fallthrough; case 0x40: case 0x41: case 0x42: diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c index a8d5d67feeaf..8698f260b988 100...

...int idx, struct nvkm_engine **); - int (*cipher )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*disp )(struct nvkm_device *, int idx, struct nvkm_disp **); - int (*dma )(struct nvkm_device *, int idx, struct nvkm_dma **); - int (*fifo )(struct nvkm_device *, int idx, struct nvkm_fifo **); - int (*gr )(struct nvkm_device *, int idx, struct nvkm_gr **); - int (*ifb )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*me )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*mpeg )(struct nvkm_device *, int idx, struct nvkm_engine **); - int (*ms...

...3ff, &node); > diff --git a/drm/nouveau/nv84_fence.c b/drm/nouveau/nv84_fence.c > index bf429cabbaa8..b981f85de888 100644 > --- a/drm/nouveau/nv84_fence.c > +++ b/drm/nouveau/nv84_fence.c > @@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm) > { > struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); > struct nv84_fence_priv *priv; > + u32 domain; > int ret; > > priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); > @@ -231,10 +232,17 @@ nv84_fence_create(struct nouveau_drm *drm) > priv-&gt...