search for: nvkm_falconidx

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

...drm/nouveau/include/nvkm/engine/falcon.h b/drm/nouveau/include/nvkm/engine/falcon.h index e6baf039c269..cfbef43586cd 100644 --- a/drm/nouveau/include/nvkm/engine/falcon.h +++ b/drm/nouveau/include/nvkm/engine/falcon.h @@ -4,13 +4,39 @@ #include <core/engine.h> struct nvkm_fifo_chan; +enum nvkm_falconidx { + NVKM_FALCON_PMU = 0, + NVKM_FALCON_RESERVED = 1, + NVKM_FALCON_FECS = 2, + NVKM_FALCON_GPCCS = 3, + NVKM_FALCON_NVDEC = 4, + NVKM_FALCON_SEC2 = 7, + NVKM_FALCON_END = 11, + NVKM_FALCON_INVALID = 0xffffffff, +}; + +enum nvkm_falcon_dmaidx { + FALCON_DMAIDX_UCODE = 0, + FALCON_DMAIDX_VIRT = 1...

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

...*, struct ls_ucode_img *); - /** * ls_ucode_img_load() - create a lsf_ucode_img and load it */ -static struct ls_ucode_img * -ls_ucode_img_load(const struct nvkm_subdev *subdev, lsf_load_func load_func) +struct ls_ucode_img * +acr_r352_ls_ucode_img_load(const struct acr_r352 *acr, + enum nvkm_falconidx falcon_id) { - struct ls_ucode_img *img; + const struct nvkm_subdev *subdev = acr->base.subdev; + struct ls_ucode_img_r352 *img; int ret; img = kzalloc(sizeof(*img), GFP_KERNEL); if (!img) return ERR_PTR(-ENOMEM); - ret = load_func(subdev, img); + img->base.falcon_id = falcon_id...

..._desc: loaded or generated map of ucode_data - * @ucode_header: header of the firmware * @ucode_data: firmware payload (code and data) * @ucode_size: size in bytes of data in ucode_data * @wpr_header: WPR header to be written to the LS blob @@ -188,7 +187,6 @@ struct ls_ucode_img { enum nvkm_falconidx falcon_id; struct ls_ucode_img_desc ucode_desc; - u32 *ucode_header; u8 *ucode_data; u32 ucode_size; diff --git a/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c b/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c index 09f5f1f1a50d..1c32cb0f16f9 100644 --- a/drm/nouveau/nvkm/subdev/secboot/ls_...

...e LS blob - * @lsb_header: LSB header to be written to the LS blob - * - * Preparing the WPR LS blob requires information about all the LS firmwares - * (size, etc) to be known. This structure contains all the data of one LS - * firmware. - */ -struct ls_ucode_img { - struct list_head node; - enum nvkm_falconidx falcon_id; - - struct ls_ucode_img_desc ucode_desc; - u32 *ucode_header; - u8 *ucode_data; - u32 ucode_size; - - struct lsf_wpr_header wpr_header; - struct lsf_lsb_header lsb_header; -}; - /** * struct ls_ucode_mgr - manager for all LS falcon firmwares * @count: number of managed LS falcons @@...

...ma.offset; - desc->data_dma_base.lo = lower_32_bits(vma_addr); - desc->data_dma_base.hi = upper_32_bits(vma_addr); + goto end; +end: /* We don't need the ACR firmware anymore */ nvkm_gpuobj_unmap(&vma); @@ -1171,15 +1163,13 @@ gm200_secboot_reset(struct nvkm_secboot *sb, enum nvkm_falconidx falcon) /* If WPR is set and we have an unload blob, run it to unlock WPR */ if (gsb->acr_unload_blob && gsb->falcon_state[NVKM_FALCON_FECS] != NON_SECURE) { - ret = gm200_secboot_run_hs_blob(gsb, gsb->acr_unload_blob, - &gsb->acr_unload_bl_desc); + ret = gm...