search for: nvkm_falcon_gpccs

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

...ot;fecs", NVKM_FALCON_FECS); } -static int -ls_ucode_img_load_gpccs(struct nvkm_subdev *subdev, struct ls_ucode_img *img) +int +gm200_ls_load_gpccs(const struct nvkm_subdev *subdev, struct ls_ucode_img *img) { return ls_ucode_img_load_generic(subdev, img, "gpccs", NVKM_FALCON_GPCCS); @@ -555,14 +386,8 @@ ls_ucode_img_load(struct nvkm_subdev *subdev, lsf_load_func load_func) return img; } -static const lsf_load_func lsf_load_funcs[] = { - [NVKM_FALCON_END] = NULL, /* reserve enough space */ - [NVKM_FALCON_FECS] = ls_ucode_img_load_fecs, - [NVKM_FALCON_GPCCS] = ls_ucode_im...

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

...acr_r352_generate_hs_bl_desc, .hs_bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc), + .ls_ucode_img_load = acr_r352_ls_ucode_img_load, + .ls_fill_headers = acr_r352_ls_fill_headers, + .ls_write_wpr = acr_r352_ls_write_wpr, .ls_func = { [NVKM_FALCON_FECS] = &acr_r352_ls_fecs_func, [NVKM_FALCON_GPCCS] = &acr_r352_ls_gpccs_func, diff --git a/drm/nouveau/nvkm/subdev/secboot/acr_r352.h b/drm/nouveau/nvkm/subdev/secboot/acr_r352.h index f6068404ba98..b2a4b2ec9af5 100644 --- a/drm/nouveau/nvkm/subdev/secboot/acr_r352.h +++ b/drm/nouveau/nvkm/subdev/secboot/acr_r352.h @@ -23,11 +23,116 @@ #defin...

...039c269..cfbef43586cd 100644 --- a/drm/nouveau/include/nvkm/engine/falcon.h +++ b/drm/nouveau/include/nvkm/engine/falcon.h @@ -4,13 +4,39 @@ #include <core/engine.h> struct nvkm_fifo_chan; +enum nvkm_falconidx { + NVKM_FALCON_PMU = 0, + NVKM_FALCON_RESERVED = 1, + NVKM_FALCON_FECS = 2, + NVKM_FALCON_GPCCS = 3, + NVKM_FALCON_NVDEC = 4, + NVKM_FALCON_SEC2 = 7, + NVKM_FALCON_END = 11, + NVKM_FALCON_INVALID = 0xffffffff, +}; + +enum nvkm_falcon_dmaidx { + FALCON_DMAIDX_UCODE = 0, + FALCON_DMAIDX_VIRT = 1, + FALCON_DMAIDX_PHYS_VID = 2, + FALCON_DMAIDX_PHYS_SYS_COH = 3, + FALCON_DMAIDX_PHYS_SYS_NCOH =...

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,