search for: nvkm_falcon

Falcon processors are used in various places of GPU chips. Although there exist different versions of the falcon, and some variants exist, the base set of actions performed on them is the same, which results in lots of duplicated code. This patch consolidates the current nvkm_falcon structure and extends it with the following features: * Ability for an engine to obtain and later release a given falcon, * Abstractions for basic operations (IMEM/DMEM access, start, etc) * Abstractions for secure operations if a falcon is secure Abstractions make it easy to e.g. start a falcon,...

...xes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon structure as a basis. Note that this currently makes struct nvkm_falcon used for two different purposes: this fact is acknowledged, and temporary. It just makes it easier to review this first step. Using the library, falcons are now acquired by a given subdev using nvkm_falcon_get(), and released...

...xes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon structure as a basis. Note that this currently makes struct nvkm_falcon used for two different purposes: this fact is acknowledged, and temporary. It just makes it easier to review this first step. Using the library, falcons are now acquired by a given subdev using nvkm_falcon_get(), and released...

...y_to(wpr_blob, pos, &img->wpr_header, sizeof(img->wpr_header)); @@ -447,6 +460,8 @@ acr_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs, nvkm_done(wpr_blob); + kfree(gdesc); + return 0; } @@ -771,7 +786,11 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon, struct fw_bl_desc *hsbl_desc; void *bl, *blob_data, *hsbl_code, *hsbl_data; u32 code_size; - u8 bl_desc[bl_desc_size]; + u8 *bl_desc; + + bl_desc = kzalloc(bl_desc_size, GFP_KERNEL); + if (!bl_desc) + return -ENOMEM; /* Find the bootloader descriptor for our blob and copy it */...

.../subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index d02e183..5c14d6a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -801,6 +801,7 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon, bl = acr->hsbl_unload_blob; } else { nvkm_error(_acr->subdev, "invalid secure boot blob!\n"); + kfree(bl_desc); return -EINVAL; } -- 2.7.4

...eau/nvkm/subdev/secboot/ls_ucode_msgqueue.c index 6f10b09..2da147b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c @@ -80,12 +80,12 @@ acr_ls_msgqueue_post_run(struct nvkm_msgqueue *queue, struct nvkm_falcon *falcon, u32 addr_args) { struct nvkm_device *device = falcon->owner->device; - u32 cmdline_size = NVKM_MSGQUEUE_CMDLINE_SIZE; - u8 buf[cmdline_size]; + u8 buf[NVKM_MSGQUEUE_CMDLINE_SIZE]; - memset(buf, 0, cmdline_size); + memset(buf, 0, NVKM_MSGQUEUE_CMDLINE_SIZE); nvkm_msgqueue_write...

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot:

...(img->wpr_header)); > @@ -447,6 +460,8 @@ acr_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs, > > nvkm_done(wpr_blob); > > + kfree(gdesc); > + > return 0; > } > > @@ -771,7 +786,11 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon, > struct fw_bl_desc *hsbl_desc; > void *bl, *blob_data, *hsbl_code, *hsbl_data; > u32 code_size; > - u8 bl_desc[bl_desc_size]; > + u8 *bl_desc; > + > + bl_desc = kzalloc(bl_desc_size, GFP_KERNEL); > + if (!bl_desc) &gt...

.../gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c >> index d02e183..5c14d6a 100644 >> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c >> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c >> @@ -801,6 +801,7 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon, >> bl = acr->hsbl_unload_blob; >> } else { >> nvkm_error(_acr->subdev, "invalid secure boot blob!\n"); >> + kfree(bl_desc); >> return -EINVAL; >> } >> >> Hi Gustavo, Seeing as how I've been working on thi...

Have an instance of nvkm_falcon in the PMU structure, ready to be used by other subdevs (i.e. secboot). Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/include/nvkm/subdev/pmu.h | 2 ++ drm/nouveau/nvkm/subdev/pmu/base.c | 4 ++++ 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/...

...vers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c index 6d5a13e4a857..82571032a07d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c @@ -52,8 +52,13 @@ gm20b_pmu_acr_bootstrap_falcon(struct nvkm_falcon *falcon, ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr, gm20b_pmu_acr_bootstrap_falcon_cb, &pmu->subdev, msecs_to_jiffies(1000)); - if (ret >= 0 && ret != cmd.falcon_id) - ret = -EIO; + if (ret >= 0) { + if (ret != cmd.falcon_id) + ret = -EIO...

...ev/secboot/gp102.c 46 static int 47 gp102_run_secure_scrub(struct nvkm_secboot *sb) 48 { 49 struct nvkm_subdev *subdev = &sb->subdev; 50 struct nvkm_device *device = subdev->device; 51 struct nvkm_engine *engine; 52 struct nvkm_falcon *falcon; 53 void *scrub_image; 54 struct fw_bin_header *hsbin_hdr; 55 struct hsf_fw_header *fw_hdr; 56 struct hsf_load_header *lhdr; 57 void *scrub_data; 58 int ret; 59 60 nvkm_debug(subdev, "runni...

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

...t;> index 6f10b09..2da147b 100644 >> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c >> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c >> @@ -80,12 +80,12 @@ acr_ls_msgqueue_post_run(struct nvkm_msgqueue *queue, >> struct nvkm_falcon *falcon, u32 addr_args) >> { >> struct nvkm_device *device = falcon->owner->device; >> - u32 cmdline_size = NVKM_MSGQUEUE_CMDLINE_SIZE; >> - u8 buf[cmdline_size]; >> + u8 buf[NVKM_MSGQUEUE_CMDLINE_SIZE]; >> >> - memset(buf, 0, cmdline_size); >...

...r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c > index d02e183..5c14d6a 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c > @@ -801,6 +801,7 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon, > bl = acr->hsbl_unload_blob; > } else { > nvkm_error(_acr->subdev, "invalid secure boot blob!\n"); > + kfree(bl_desc); > return -EINVAL; > } > >

.../nvkm/subdev/secboot/acr_r352.c >>> index d02e183..5c14d6a 100644 >>> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c >>> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c >>> @@ -801,6 +801,7 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon, >>> bl = acr->hsbl_unload_blob; >>> } else { >>> nvkm_error(_acr->subdev, "invalid secure boot blob!\n"); >>> + kfree(bl_desc); >>> return -EINVAL; >>> } >&g...

...s_ucode_msgqueue.c > index 6f10b09..2da147b 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c > @@ -80,12 +80,12 @@ acr_ls_msgqueue_post_run(struct nvkm_msgqueue *queue, > struct nvkm_falcon *falcon, u32 addr_args) > { > struct nvkm_device *device = falcon->owner->device; > - u32 cmdline_size = NVKM_MSGQUEUE_CMDLINE_SIZE; > - u8 buf[cmdline_size]; > + u8 buf[NVKM_MSGQUEUE_CMDLINE_SIZE]; > > - memset(buf, 0, cmdline_size); > + memset(buf, 0, NVKM_MSGQUE...

...index 62c5e162099a..280b1448df88 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h > @@ -41,6 +41,6 @@ int gm200_secboot_run_blob(struct nvkm_secboot *, struct nvkm_gpuobj *, > struct nvkm_falcon *); > > /* Tegra-only */ > -int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *, u32); > +int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *); > > #endif > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/...

...can also come up with a patch by next > >>>> week. > >>>> > >>> Well, I'd love to but a quick glance at the code caused me to bump into this obscenity: > >>> > >>> int > >>> gm200_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *falcon) > >>> { > >>> nvkm_falcon_mask(falcon, 0x040, 0x00000000, 0x00000000); > >>> > >>> if (nvkm_msec(falcon->owner->device, 10, > >>> if (!(nvkm_falcon_rd32(falcon, 0x10c) & 0x00000006)) >...

...eau/nvkm/subdev/secboot/ls_ucode_msgqueue.c index 6f10b09..1e1f1c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c @@ -80,12 +80,11 @@ acr_ls_msgqueue_post_run(struct nvkm_msgqueue *queue, struct nvkm_falcon *falcon, u32 addr_args) { struct nvkm_device *device = falcon->owner->device; - u32 cmdline_size = NVKM_MSGQUEUE_CMDLINE_SIZE; - u8 buf[cmdline_size]; + u8 buf[NVKM_MSGQUEUE_CMDLINE_SIZE]; - memset(buf, 0, cmdline_size); + memset(buf, 0, sizeof(buf)); nvkm_msgqueue_write_cmdline(queue,...