search for: nvkm_engine_ce1

..._SUBDEV_PCI ] = "pci", - [NVKM_SUBDEV_PMU ] = "pmu", - [NVKM_SUBDEV_THERM ] = "therm", - [NVKM_SUBDEV_TIMER ] = "tmr", - [NVKM_SUBDEV_VOLT ] = "volt", - [NVKM_ENGINE_BSP ] = "bsp", - [NVKM_ENGINE_CE0 ] = "ce0", - [NVKM_ENGINE_CE1 ] = "ce1", - [NVKM_ENGINE_CE2 ] = "ce2", - [NVKM_ENGINE_CIPHER ] = "cipher", - [NVKM_ENGINE_DISP ] = "disp", - [NVKM_ENGINE_DMAOBJ ] = "dma", - [NVKM_ENGINE_FIFO ] = "fifo", - [NVKM_ENGINE_GR ] = "gr", - [NVKM_ENGIN...

..._SUBDEV_PCI ] = "pci", - [NVKM_SUBDEV_PMU ] = "pmu", - [NVKM_SUBDEV_THERM ] = "therm", - [NVKM_SUBDEV_TIMER ] = "tmr", - [NVKM_SUBDEV_VOLT ] = "volt", - [NVKM_ENGINE_BSP ] = "bsp", - [NVKM_ENGINE_CE0 ] = "ce0", - [NVKM_ENGINE_CE1 ] = "ce1", - [NVKM_ENGINE_CE2 ] = "ce2", - [NVKM_ENGINE_CIPHER ] = "cipher", - [NVKM_ENGINE_DISP ] = "disp", - [NVKM_ENGINE_DMAOBJ ] = "dma", - [NVKM_ENGINE_FIFO ] = "fifo", - [NVKM_ENGINE_GR ] = "gr", - [NVKM_ENGIN...

..._SUBDEV_PCI ] = "pci", - [NVKM_SUBDEV_PMU ] = "pmu", - [NVKM_SUBDEV_THERM ] = "therm", - [NVKM_SUBDEV_TIMER ] = "tmr", - [NVKM_SUBDEV_VOLT ] = "volt", - [NVKM_ENGINE_BSP ] = "bsp", - [NVKM_ENGINE_CE0 ] = "ce0", - [NVKM_ENGINE_CE1 ] = "ce1", - [NVKM_ENGINE_CE2 ] = "ce2", - [NVKM_ENGINE_CIPHER ] = "cipher", - [NVKM_ENGINE_DISP ] = "disp", - [NVKM_ENGINE_DMAOBJ ] = "dma", - [NVKM_ENGINE_FIFO ] = "fifo", - [NVKM_ENGINE_GR ] = "gr", - [NVKM_ENGIN...

The INA3221 is usually found on mid and high end kepler+ gpus Marins Patch implements the new iccsense subdev and all needed bits for the INA3221 power sensor. My Patch implements the hwmon power1 interface to expose the current power consumption through hwmon (and can be read out via sysfs or the sensors tool) Please test these patches for Fermi+ GPUs, that nothing gets messed up and works as

...subdev_name[NVKM_SUBDEV_NR] = { [NVKM_SUBDEV_THERM ] = "therm", [NVKM_SUBDEV_TIMER ] = "tmr", [NVKM_SUBDEV_VOLT ] = "volt", + [NVKM_SUBDEV_SECBOOT] = "secboot", [NVKM_ENGINE_BSP ] = "bsp", [NVKM_ENGINE_CE0 ] = "ce0", [NVKM_ENGINE_CE1 ] = "ce1", diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index b1ba1c782a2b..95fc9a69d322 100644 --- a/drm/nouveau/nvkm/engine/device/base.c +++ b/drm/nouveau/nvkm/engine/device/base.c @@ -2092,6 +2092,7 @@ nvkm_device_subdev(struct nvkm_dev...

This is a complete rework from the first version I sent out. Now the implementation is more centered around the power_rails we find in the SENSE table instead of extdev centered. This makes the implementation a lot easier and straightforward. I've added support for the INA219, INA209 and INA3221 sensors found on multiple Fermi and Kepler cards. The power consumption is also exported via

This is a complete rework from the last version I sent out. Now the implementation is more centered around the power_rails we find in the SENSE table instead of extdev centered. This makes the implementation a lot easier and straightforward. I've added support for the INA219, INA209 and INA3221 sensors found on multiple Fermi and Kepler cards, but only the INA3221 bits are tested so far.

This is a complete rework from the first version I sent out. Now the implementation is more centered around the power_rails we find in the SENSE table instead of extdev centered. This makes the implementation a lot easier and straightforward. I've added support for the INA219, INA209 and INA3221 sensors found on multiple Fermi and Kepler cards. The power consumption is also exported via

This is a complete rework from the first version I sent out. Now the implementation is more centered around the power_rails we find in the SENSE table instead of extdev centered. This makes the implementation a lot easier and straightforward. I've added support for the INA219, INA209 and INA3221 sensors found on multiple Fermi and Kepler cards. The power consumption is also exported via

...v.h" + +int +gf100_clkgate_engine(enum nvkm_devidx subdev) +{ + switch (subdev) { + case NVKM_ENGINE_GR: return 0x00; + case NVKM_ENGINE_MSPDEC: return 0x04; + case NVKM_ENGINE_MSPPP: return 0x08; + case NVKM_ENGINE_MSVLD: return 0x0c; + case NVKM_ENGINE_CE0: return 0x10; + case NVKM_ENGINE_CE1: return 0x14; + case NVKM_ENGINE_MSENC: return 0x18; + case NVKM_ENGINE_CE2: return 0x1c; + default: return -1; + } +} + +void +gf100_clkgate_set(struct nvkm_therm *therm, int gate_idx, bool enable) +{ + u8 data; + + if (enable) /* ENG_CLK=auto, BLK_CLK=auto, ENG_PWR=run,...

...return 0x00; > > +               case NVKM_ENGINE_MSPDEC: return 0x04; > > +               case NVKM_ENGINE_MSPPP:  return 0x08; > > +               case NVKM_ENGINE_MSVLD:  return 0x0c; > > +               case NVKM_ENGINE_CE0:    return 0x10; > > +               case NVKM_ENGINE_CE1:    return 0x14; > > +               case NVKM_ENGINE_MSENC:  return 0x18; > > +               case NVKM_ENGINE_CE2:    return 0x1c; > > +               default:                 return -1; > > +       } > > +} > > + > > +void > > +gf100_clkgate_set(st...

...nline int +gf100_clkgate_engine_offset(enum nvkm_devidx subdev) +{ + switch (subdev) { + case NVKM_ENGINE_GR: return 0x00; + case NVKM_ENGINE_MSPDEC: return 0x04; + case NVKM_ENGINE_MSPPP: return 0x08; + case NVKM_ENGINE_MSVLD: return 0x0c; + case NVKM_ENGINE_CE0: return 0x10; + case NVKM_ENGINE_CE1: return 0x14; + case NVKM_ENGINE_MSENC: return 0x18; + case NVKM_ENGINE_CE2: return 0x1c; + default: return -1; + } +} + +void +gf100_clkgate_engine(struct nvkm_therm *therm, enum nvkm_devidx subdev, + bool enable) +{ + int offset = gf100_clkgate_engine_offset(subdev...

...case NVKM_ENGINE_GR: return 0x00; > + case NVKM_ENGINE_MSPDEC: return 0x04; > + case NVKM_ENGINE_MSPPP: return 0x08; > + case NVKM_ENGINE_MSVLD: return 0x0c; > + case NVKM_ENGINE_CE0: return 0x10; > + case NVKM_ENGINE_CE1: return 0x14; > + case NVKM_ENGINE_MSENC: return 0x18; > + case NVKM_ENGINE_CE2: return 0x1c; > + default: return -1; > + } > +} > + > +void > +gf100_clkgate_set(struct nvkm_therm *therm, int gate_idx, bo...

...onst struct gk104_clkgate_engine_info gk104_clkgate_engine_info[] = { > + { NVKM_ENGINE_GR, 0x00 }, > + { NVKM_ENGINE_MSPDEC, 0x04 }, > + { NVKM_ENGINE_MSPPP, 0x08 }, > + { NVKM_ENGINE_MSVLD, 0x0c }, > + { NVKM_ENGINE_CE0, 0x10 }, > + { NVKM_ENGINE_CE1, 0x14 }, > + { NVKM_ENGINE_MSENC, 0x18 }, > + { NVKM_ENGINE_CE2, 0x1c }, > + { NVKM_SUBDEV_NR, 0 }, > +}; > + > +const struct gf100_idle_filter gk104_idle_filter = { > + .fecs = 0x00001000, > + .hubmmu = 0x00001000, > +}; > + > +...

...nvkm_mask(dev, 0x20200 + order[i].offset, 0xff, 0x54); + } +} + +const struct gk104_clkgate_engine_info gk104_clkgate_engine_info[] = { + { NVKM_ENGINE_GR, 0x00 }, + { NVKM_ENGINE_MSPDEC, 0x04 }, + { NVKM_ENGINE_MSPPP, 0x08 }, + { NVKM_ENGINE_MSVLD, 0x0c }, + { NVKM_ENGINE_CE0, 0x10 }, + { NVKM_ENGINE_CE1, 0x14 }, + { NVKM_ENGINE_MSENC, 0x18 }, + { NVKM_ENGINE_CE2, 0x1c }, + { NVKM_SUBDEV_NR, 0 }, +}; + +const struct gf100_idle_filter gk104_idle_filter = { + .fecs = 0x00001000, + .hubmmu = 0x00001000, +}; + +static const struct nvkm_therm_func +gk104_therm_func = { + .init = gf119_therm_init,...

...nvkm_mask(dev, 0x20200 + order[i].offset, 0xff, 0x54); + } +} + +const struct gk104_clkgate_engine_info gk104_clkgate_engine_info[] = { + { NVKM_ENGINE_GR, 0x00 }, + { NVKM_ENGINE_MSPDEC, 0x04 }, + { NVKM_ENGINE_MSPPP, 0x08 }, + { NVKM_ENGINE_MSVLD, 0x0c }, + { NVKM_ENGINE_CE0, 0x10 }, + { NVKM_ENGINE_CE1, 0x14 }, + { NVKM_ENGINE_MSENC, 0x18 }, + { NVKM_ENGINE_CE2, 0x1c }, + { NVKM_SUBDEV_NR, 0 }, +}; + +const struct gf100_idle_filter gk104_idle_filter = { + .fecs = 0x00001000, + .hubmmu = 0x00001000, +}; + +static const struct nvkm_therm_func +gk104_therm_func = { + .init = gf119_therm_init,...

...nvkm_mask(dev, 0x20200 + order[i].offset, 0xff, 0x54); + } +} + +const struct gk104_clkgate_engine_info gk104_clkgate_engine_info[] = { + { NVKM_ENGINE_GR, 0x00 }, + { NVKM_ENGINE_MSPDEC, 0x04 }, + { NVKM_ENGINE_MSPPP, 0x08 }, + { NVKM_ENGINE_MSVLD, 0x0c }, + { NVKM_ENGINE_CE0, 0x10 }, + { NVKM_ENGINE_CE1, 0x14 }, + { NVKM_ENGINE_MSENC, 0x18 }, + { NVKM_ENGINE_CE2, 0x1c }, + { NVKM_SUBDEV_NR, 0 }, +}; + +const struct gf100_idle_filter gk104_idle_filter = { + .fecs = 0x00001000, + .hubmmu = 0x00001000, +}; + +static const struct nvkm_therm_func +gk104_therm_func = { + .init = gf119_therm_init,...

...num nvkm_devidx subdev) > +{ > + switch (subdev) { > + case NVKM_ENGINE_GR: return 0x00; > + case NVKM_ENGINE_MSPDEC: return 0x04; > + case NVKM_ENGINE_MSPPP: return 0x08; > + case NVKM_ENGINE_MSVLD: return 0x0c; > + case NVKM_ENGINE_CE0: return 0x10; > + case NVKM_ENGINE_CE1: return 0x14; > + case NVKM_ENGINE_MSENC: return 0x18; > + case NVKM_ENGINE_CE2: return 0x1c; > + default: return -1; > + } > +} > + > +void > +gf100_clkgate_set(struct nvkm_therm *therm, int gate_idx, bool enable) > +{ > + u8 data; > + &gt...

Next version of my patchseries for adding clockgating support for kepler1 and 2 on nouveau. The first version of this series can be found here: https://patchwork.freedesktop.org/series/36504/ Some minor changes: - Clarified that SLCG stands for 'secondary level clockgating', thanks for the small tip nvidia! - Removed the concept of levels, this was more useful for debugging then

It's here! After a lot of investigation, rewrites, and traces, I present the patch series to implement all known levels of clockgating for Kepler1 and Kepler2 GPUs. Starting with Fermi GPUs (this is probably present on earlier GPUs as well, but with a far less easy to manage interface), nvidia added two clockgating levels that are handled mostly in firmware (with the exception of course, of