search for: nvkm_domain

...changed, 42 insertions(+), 4 deletions(-) diff --git a/drm/nouveau/include/nvkm/subdev/clk.h b/drm/nouveau/include/nvkm/subdev/clk.h index 6226f0d..99ee05c 100644 --- a/drm/nouveau/include/nvkm/subdev/clk.h +++ b/drm/nouveau/include/nvkm/subdev/clk.h @@ -68,7 +68,8 @@ struct nvkm_pstate { struct nvkm_domain { enum nv_clk_src name; u8 bios; /* 0xff for none */ -#define NVKM_CLK_DOM_FLAG_CORE 0x01 +#define NVKM_CLK_DOM_FLAG_CORE 0x01 +#define NVKM_CLK_DOM_FLAG_BASECLK 0x02 u8 flags; const char *mname; int mdiv; @@ -98,6 +99,12 @@ struct nvkm_clk { int dstate; /* display adjustment (min+)...

This patch set includes two instances where the list iterator variable 'pstate' is implicitly assumed to be valid after the iterator loop. While in pratice that is most likely the case (if 'pstatei'/'args->v0.state' is <= the elements in clk->states), we should explicitly only allow 'pstate' to always point to correct 'nvkm_pstate' structs. That

...ions(-) > > diff --git a/drm/nouveau/include/nvkm/subdev/clk.h b/drm/nouveau/include/nvkm/subdev/clk.h > index 8708f0a..8085d81 100644 > --- a/drm/nouveau/include/nvkm/subdev/clk.h > +++ b/drm/nouveau/include/nvkm/subdev/clk.h > @@ -64,7 +64,8 @@ struct nvkm_pstate { > struct nvkm_domain { > enum nv_clk_src name; > u8 bios; /* 0xff for none */ > -#define NVKM_CLK_DOM_FLAG_CORE 0x01 > +#define NVKM_CLK_DOM_FLAG_CORE 0x01 > +#define NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE 0x02 > u8 flags; > const char *mname; > int mdiv; > @@ -94,6 +95,13 @@...

.../drm/nouveau/nvkm/engine/device/ctrl.c > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c > @@ -72,7 +72,7 @@ nvkm_control_mthd_pstate_attr(struct nvkm_control *ctrl, void *data, u32 size) > } *args = data; > struct nvkm_clk *clk = ctrl->device->clk; > const struct nvkm_domain *domain; > - struct nvkm_pstate *pstate; > + struct nvkm_pstate *pstate = NULL, *iter; > struct nvkm_cstate *cstate; > int i = 0, j = -1; > u32 lo, hi; > @@ -103,11 +103,14 @@ nvkm_control_mthd_pstate_attr(struct nvkm_control *ctrl, void *data, u32 size) > return -EINV...

this series solves different issues we encounter on kepler cards while reclocking: 1. core clock doesn't change at all and produces a volting error (patch 1) this can happen when the voltage table has only 0ed values in the header so we have to parse the entries itself, which contain the right voltages 2. kepler won't clock to highest cstates (patch 2) this happens, because there are

...changed, 27 insertions(+), 4 deletions(-) diff --git a/drm/nouveau/include/nvkm/subdev/clk.h b/drm/nouveau/include/nvkm/subdev/clk.h index 8708f0a..8085d81 100644 --- a/drm/nouveau/include/nvkm/subdev/clk.h +++ b/drm/nouveau/include/nvkm/subdev/clk.h @@ -64,7 +64,8 @@ struct nvkm_pstate { struct nvkm_domain { enum nv_clk_src name; u8 bios; /* 0xff for none */ -#define NVKM_CLK_DOM_FLAG_CORE 0x01 +#define NVKM_CLK_DOM_FLAG_CORE 0x01 +#define NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE 0x02 u8 flags; const char *mname; int mdiv; @@ -94,6 +95,13 @@ struct nvkm_clk { int dstate; /* display ad...

...changed, 34 insertions(+), 5 deletions(-) diff --git a/drm/nouveau/include/nvkm/subdev/clk.h b/drm/nouveau/include/nvkm/subdev/clk.h index fb54417..a292e5a 100644 --- a/drm/nouveau/include/nvkm/subdev/clk.h +++ b/drm/nouveau/include/nvkm/subdev/clk.h @@ -67,7 +67,8 @@ struct nvkm_pstate { struct nvkm_domain { enum nv_clk_src name; u8 bios; /* 0xff for none */ -#define NVKM_CLK_DOM_FLAG_CORE 0x01 +#define NVKM_CLK_DOM_FLAG_CORE 0x01 +#define NVKM_CLK_DOM_FLAG_BASECLK 0x02 u8 flags; const char *mname; int mdiv; @@ -97,6 +98,12 @@ struct nvkm_clk { int dstate; /* display adjustment (min+)...

...func { int (*calc)(struct nvkm_clk *, struct nvkm_cstate *); int (*prog)(struct nvkm_clk *); void (*tidy)(struct nvkm_clk *); - void (*update)(struct nvkm_clk *, int pstate); + void (*update)(struct nvkm_clk *, int pstate, bool force); struct nvkm_pstate *pstates; int nr_pstates; struct nvkm_domain domains[]; @@ -30,6 +30,6 @@ int nv04_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, int clk, struct nvkm_pll_vals *); int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *); -void nv40_clk_update(struct nvkm_clk *, int pstate); -void gf100_clk_update(struct nv...

...m/nouveau/include/nvkm/subdev/clk.h > > b/drm/nouveau/include/nvkm/subdev/clk.h > > index 8708f0a..8085d81 100644 > > --- a/drm/nouveau/include/nvkm/subdev/clk.h > > +++ b/drm/nouveau/include/nvkm/subdev/clk.h > > @@ -64,7 +64,8 @@ struct nvkm_pstate { > > struct nvkm_domain { > > enum nv_clk_src name; > > u8 bios; /* 0xff for none */ > > -#define NVKM_CLK_DOM_FLAG_CORE 0x01 > > +#define NVKM_CLK_DOM_FLAG_CORE 0x01 > > +#define NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE 0x02 > > u8 flags; > > const char *mname; > > int mdiv; >...

With these both patches, most of the kepler cards should be able to reclock their core clock without issues. These patches should be tested carefully among nouveau devs, so that these don't break reclocking on other cards (especially Teslas). Particularly the second one might break reclocking here and there. Karol Herbst (2): bios/volt: handle voltage table version 0x50 with 0ed header

...eau/nvkm/subdev/clk/priv.h @@ -10,6 +10,7 @@ struct nvkm_clk_func { int (*calc)(struct nvkm_clk *, struct nvkm_cstate *); int (*prog)(struct nvkm_clk *); void (*tidy)(struct nvkm_clk *); + void (*update)(struct nvkm_clk *, int pstate); struct nvkm_pstate *pstates; int nr_pstates; struct nvkm_domain domains[]; @@ -20,7 +21,11 @@ int nvkm_clk_ctor(const struct nvkm_clk_func *, struct nvkm_device *, int, int nvkm_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, int, bool allow_reclock, struct nvkm_clk **); +int nvkm_pstate_prog(struct nvkm_clk *, int pstateid); + int nv04_cl...

this series solves different issues we encounter on kepler cards while reclocking: 1. core clock doesn't change at all and produces a volting error (patch 1) this can happen when the voltage table has only 0ed values in the header so we have to parse the entries itself, which contain the right voltages 2. kepler won't clock to highest cstates (patch 2) this happens, because there are

This series fixes most of the issues regarding volting on GPUs with any form of GPU Boost inside their vbios, which is mainly Kepler and newer, but we find some boosting related tables in Fermi vbios' already In the end reclocking should work on most Kepler cards without any issues Karol Herbst (19): bios/volt: handle voltage table version 0x50 with 0ed header volt: properly detect entry

We are slowly getting there! v4 of the series with some realy good improvements, so I am sure this is like 95% done and only needs some proper polishing and proper Reviews! I also added the NvVoltOffsetmV module parameter, so that a user is able to over and !under!-volt the GPU. Overvolting makes sense, when there are still some reclocking issues left, which might be solved by a higher voltage.

This series fixes most of the issues regarding volting on GPUs with any form of GPU Boost inside their vbios, which is mainly Kepler and newer, but we find some boosting related tables in Fermi vbios' already In the end reclocking should work on most Kepler cards without any issues v2: boost_mode can now be changed at runtime minor fixups Karol Herbst (22): bios/volt: handle voltage

I've splitted my big series between the part which actually fixes the engine reclocking bits and the part handling voltage/clock updates on temperature change, so that the more reviewed parts can be merged in faster. This series fixes a lot of Engine reclocking issues found on Fermi, Kepler and all Maxwell generation GPUs. It does _not_ fix memory reclocking on Fermi. It mostly contains of

This is an updated series for the old clocking improvement one. I think I got everything needed in place and also a simple update mechanism for updating the cstates/voltage on temperature changes. If anything is unclear how I REed or got the information, please leave a note so that I can provide additional information in the commits. Besides that I think we are pretty close now and only some

Last update here: https://lists.freedesktop.org/archives/nouveau/2017-September/028848.html Basically big cleanup, reordering, simplifications and some renaming to make the code easier to read and to review. I also moved some bugfixes to the front so they can be merged prior the other patches. There was also a bug related to the therm daemon triggering a pstate change leading to PMU lockups,

overall it is for the most part the same as my older version. I cleaned up some copyright things, so that it is more like the others. Also I moved the print about the max speed supported into preinit and did some other minor cleanups in the 3rd commit. Happy testing (and performance for prime offloading setups) Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement

this patch series implements PCIe speed changes for Tesla and newer. The Kepler and Fermi bits are tested on my cards at home. Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement generic code for PCIe speed change pci: implement pcie speed change for tesla pci: implement pcie speed change on Fermi pci: implement PCIe speed change for kepler+ bios/perf: