Displaying 5 results from an estimated 5 matches for "nvkm_clk_dom_flag_base_clock_core".
2015 Dec 02
2
[RFC PATCH 5/5] clk: allow boosting only when NvBoost is set
...clk.h
> +++ b/drm/nouveau/include/nvkm/subdev/clk.h
> @@ -64,7 +64,8 @@ struct nvkm_pstate {
> struct nvkm_domain {
> enum nv_clk_src name;
> u8 bios; /* 0xff for none */
> -#define NVKM_CLK_DOM_FLAG_CORE 0x01
> +#define NVKM_CLK_DOM_FLAG_CORE 0x01
> +#define NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE 0x02
> u8 flags;
> const char *mname;
> int mdiv;
> @@ -94,6 +95,13 @@ struct nvkm_clk {
> int dstate; /* display adjustment (min+) */
>
> bool allow_reclock;
> +#define NVKM_CLK_BOOST_MODE_NONE 0x0
> +#define NVKM_CLK_BOOST_MODE_AVG 0x1
> +#define NVKM_CL...
2015 Dec 01
0
[RFC PATCH 5/5] clk: allow boosting only when NvBoost is set
...4
--- a/drm/nouveau/include/nvkm/subdev/clk.h
+++ b/drm/nouveau/include/nvkm/subdev/clk.h
@@ -64,7 +64,8 @@ struct nvkm_pstate {
struct nvkm_domain {
enum nv_clk_src name;
u8 bios; /* 0xff for none */
-#define NVKM_CLK_DOM_FLAG_CORE 0x01
+#define NVKM_CLK_DOM_FLAG_CORE 0x01
+#define NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE 0x02
u8 flags;
const char *mname;
int mdiv;
@@ -94,6 +95,13 @@ struct nvkm_clk {
int dstate; /* display adjustment (min+) */
bool allow_reclock;
+#define NVKM_CLK_BOOST_MODE_NONE 0x0
+#define NVKM_CLK_BOOST_MODE_AVG 0x1
+#define NVKM_CLK_BOOST_MODE_FULL 0x2
+ u8 boost_mode;
+
+ u32 bas...
2015 Dec 02
0
[RFC PATCH 5/5] clk: allow boosting only when NvBoost is set
...m/nouveau/include/nvkm/subdev/clk.h
> > @@ -64,7 +64,8 @@ struct nvkm_pstate {
> > struct nvkm_domain {
> > enum nv_clk_src name;
> > u8 bios; /* 0xff for none */
> > -#define NVKM_CLK_DOM_FLAG_CORE 0x01
> > +#define NVKM_CLK_DOM_FLAG_CORE 0x01
> > +#define NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE 0x02
> > u8 flags;
> > const char *mname;
> > int mdiv;
> > @@ -94,6 +95,13 @@ struct nvkm_clk {
> > int dstate; /* display adjustment (min+) */
> >
> > bool allow_reclock;
> > +#define NVKM_CLK_BOOST_MODE_NONE 0x0
> > +#define NVKM_CLK_BOOST_M...
2015 Dec 01
7
[RFC PATCH 0/5] stabilize kepler reclocking
this series solves different issues we encounter on kepler cards while reclocking:
1. core clock doesn't change at all and produces a volting error (patch 1)
this can happen when the voltage table has only 0ed values in the header
so we have to parse the entries itself, which contain the right voltages
2. kepler won't clock to highest cstates (patch 2)
this happens, because there are
2015 Dec 02
11
[RFC PATCH v2 0/7] stabilize kepler reclocking
this series solves different issues we encounter on kepler cards while reclocking:
1. core clock doesn't change at all and produces a volting error (patch 1)
this can happen when the voltage table has only 0ed values in the header
so we have to parse the entries itself, which contain the right voltages
2. kepler won't clock to highest cstates (patch 2)
this happens, because there are