search for: nvkm_clk_adjust

...x df9173e..ae76601 100644 > --- a/drm/nouveau/nvkm/subdev/clk/base.c > +++ b/drm/nouveau/nvkm/subdev/clk/base.c > @@ -166,6 +166,12 @@ nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate) > if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { > u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate, > domain->bios, cstepX.freq); > + if (domain->flags & NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE) { > + if (clk->boost_mode == 0 && freq > clk->base_clock) > + goto err; > + if (clk->boost_mode == 1 && f...

...git a/drm/nouveau/nvkm/subdev/clk/base.c b/drm/nouveau/nvkm/subdev/clk/base.c index a9a3666..1ca25dd 100644 --- a/drm/nouveau/nvkm/subdev/clk/base.c +++ b/drm/nouveau/nvkm/subdev/clk/base.c @@ -257,6 +257,8 @@ nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate) u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate, domain->bios, cstepX.freq); cstate->domain[domain->name] = freq; + if (domain->flags & NVKM_CLK_DOM_FLAG_BASECLK) + clk->max_khz = max(clk->max_khz, freq); } domain++; } -- 2.8.1

...+++++++++++++++++++++++++++----- 1 file changed, 74 insertions(+), 9 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/clk/base.c b/drm/nouveau/nvkm/subdev/clk/base.c index fecf58f..21f6369 100644 --- a/drm/nouveau/nvkm/subdev/clk/base.c +++ b/drm/nouveau/nvkm/subdev/clk/base.c @@ -74,6 +74,78 @@ nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, /****************************************************************************** * C-States *****************************************************************************/ +static bool +nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate, u32 max...

...km/subdev/clk/base.c index df9173e..ae76601 100644 --- a/drm/nouveau/nvkm/subdev/clk/base.c +++ b/drm/nouveau/nvkm/subdev/clk/base.c @@ -166,6 +166,12 @@ nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate) if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate, domain->bios, cstepX.freq); + if (domain->flags & NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE) { + if (clk->boost_mode == 0 && freq > clk->base_clock) + goto err; + if (clk->boost_mode == 1 && freq > clk->boost_cl...

...km/subdev/clk/base.c index 4928668..d575412 100644 --- a/drm/nouveau/nvkm/subdev/clk/base.c +++ b/drm/nouveau/nvkm/subdev/clk/base.c @@ -160,6 +160,18 @@ nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate) if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate, domain->bios, cstepX.freq); + if (domain->flags & NVKM_CLK_DOM_FLAG_BASECLK) { + switch (clk->boost_mode) { + case NVKM_CLK_BOOST_NONE: + if (clk->base_khz + && freq > clk->base_khz) + goto err; + case...

...e.c +++ b/drm/nouveau/nvkm/subdev/clk/base.c @@ -24,6 +24,7 @@ #include "priv.h" #include <subdev/bios.h> +#include <subdev/bios/baseclock.h> #include <subdev/bios/boost.h> #include <subdev/bios/cstep.h> #include <subdev/bios/perf.h> @@ -77,9 +78,25 @@ nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, static bool nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate, u32 max_volt, int temp) { + const struct nvkm_domain *domain = clk->domains; struct nvkm_volt *volt = clk->subdev.device->volt; int voltage; + while (domain &&amp...

...gt; --- a/drm/nouveau/nvkm/subdev/clk/base.c > > +++ b/drm/nouveau/nvkm/subdev/clk/base.c > > @@ -166,6 +166,12 @@ nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct > > nvkm_pstate *pstate) > > if (domain->flags &amp; NVKM_CLK_DOM_FLAG_CORE) { > > u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate, > > domain->bios, cstepX.freq); > > + if (domain->flags &amp; NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE) { > > + if (clk->boost_mode == 0 &amp;&amp; freq > clk->base_clock) > > + goto err; > > + if (clk->boost_mode ==...

this series solves different issues we encounter on kepler cards while reclocking: 1. core clock doesn't change at all and produces a volting error (patch 1) this can happen when the voltage table has only 0ed values in the header so we have to parse the entries itself, which contain the right voltages 2. kepler won't clock to highest cstates (patch 2) this happens, because there are

This series fixes most of the issues regarding volting on GPUs with any form of GPU Boost inside their vbios, which is mainly Kepler and newer, but we find some boosting related tables in Fermi vbios' already In the end reclocking should work on most Kepler cards without any issues Karol Herbst (19): bios/volt: handle voltage table version 0x50 with 0ed header volt: properly detect entry

This series fixes most of the issues regarding volting on GPUs with any form of GPU Boost inside their vbios, which is mainly Kepler and newer, but we find some boosting related tables in Fermi vbios' already In the end reclocking should work on most Kepler cards without any issues v2: boost_mode can now be changed at runtime minor fixups Karol Herbst (22): bios/volt: handle voltage

Last update here: https://lists.freedesktop.org/archives/nouveau/2017-September/028848.html Basically big cleanup, reordering, simplifications and some renaming to make the code easier to read and to review. I also moved some bugfixes to the front so they can be merged prior the other patches. There was also a bug related to the therm daemon triggering a pstate change leading to PMU lockups,

This is an updated series for the old clocking improvement one. I think I got everything needed in place and also a simple update mechanism for updating the cstates/voltage on temperature changes. If anything is unclear how I REed or got the information, please leave a note so that I can provide additional information in the commits. Besides that I think we are pretty close now and only some

this series solves different issues we encounter on kepler cards while reclocking: 1. core clock doesn't change at all and produces a volting error (patch 1) this can happen when the voltage table has only 0ed values in the header so we have to parse the entries itself, which contain the right voltages 2. kepler won't clock to highest cstates (patch 2) this happens, because there are

We are slowly getting there! v4 of the series with some realy good improvements, so I am sure this is like 95% done and only needs some proper polishing and proper Reviews! I also added the NvVoltOffsetmV module parameter, so that a user is able to over and !under!-volt the GPU. Overvolting makes sense, when there are still some reclocking issues left, which might be solved by a higher voltage.

I've splitted my big series between the part which actually fixes the engine reclocking bits and the part handling voltage/clock updates on temperature change, so that the more reviewed parts can be merged in faster. This series fixes a lot of Engine reclocking issues found on Fermi, Kepler and all Maxwell generation GPUs. It does _not_ fix memory reclocking on Fermi. It mostly contains of

Just wanted to post updated versions of my last series/patches. Reviews welcomed. It would be also nice if we agree on features I should focus upstreaming, so that this work can be better splitted or reordered. Sadly most of my patches depend on the rather big clk subdev rework and I think those patches shows best, why I think this rework is actually needed and makes things much easier to add