search for: nvk

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2007 Nov 09
2
[LLVMdev] Register allocation balancing issues
...eference to the PLDI paper: Balancing Register Allocation Across Threads for a Multithreaded Network Processor Xiaotong Zhuang and Santosh Pande PLDI'04 Another take (and quite not a longshot although probably Fernando -- thanks for the debugger, will try it -- has worked either alone or with NVK on the ILP formulation) is to write-up constraints for an ILP (integer linear programming) solution. I wouldn't mind to wait forever (for several minutes that is ^_^) for a valid register allocation to complete. My application programs range between 50 (the smallest) to about 2K instructions. B...
2007 Nov 09
0
[LLVMdev] Register allocation balancing issues
> > Another take (and quite not a longshot although probably Fernando -- thanks for > the debugger, will try it -- has worked either alone or with NVK on the ILP > formulation) is to write-up constraints for an ILP (integer linear programming) > solution. I wouldn't mind to wait forever (for several minutes that is ^_^) for > a valid register allocation to complete. My application programs range between > 50 (the smallest) to abou...
2007 Nov 08
0
[LLVMdev] Two labels around one instruction in Codegen
That would complicate instruction selection. Not worth it. Evan On Nov 8, 2007, at 1:10 AM, Duncan Sands wrote: >> Ok, so it turns out the labels do not have to be just before / after >> the divide. So we don't have to use the MVT::Flag hackery. However, >> the second label must be after the divide. I think the solution is to >> add a trapping version of DIV (and
2007 Nov 08
2
[LLVMdev] Two labels around one instruction in Codegen
> Ok, so it turns out the labels do not have to be just before / after > the divide. So we don't have to use the MVT::Flag hackery. However, > the second label must be after the divide. I think the solution is to > add a trapping version of DIV (and others) and the second label can > use its chain value as operand. How about a new "trapping" SDNode, which you
2024 May 09
0
[PATCH v4] drm/nouveau: use tile_mode and pte_kind for VM_BIND bo allocations
On Thu, May 9, 2024 at 3:44?PM Mohamed Ahmed < mohamedahmedegypt2001 at gmail.com> wrote: > Allows PTE kind and tile mode on BO create with VM_BIND, > and adds a GETPARAM to indicate this change. This is needed to support > modifiers in NVK and ensure correctness when dealing with the nouveau > GL driver. > > The userspace modifiers implementation this is for can be found here: > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24795 > > Fixes: b88baab82871 ("drm/nouveau: implement new VM_BIND uAPI&quot...
2024 May 08
0
[PATCH v3] drm/nouveau: use tile_mode and pte_kind for VM_BIND bo allocations
On Wed, May 8, 2024 at 6:06?PM Mohamed Ahmed < mohamedahmedegypt2001 at gmail.com> wrote: > Allows PTE kind and tile mode on BO create with VM_BIND, > and adds a GETPARAM to indicate this change. This is needed to support > modifiers in NVK and ensure correctness when dealing with the nouveau > GL driver. > > The userspace modifiers implementation this is for can be found here: > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28843 > > Fixes: b88baab82871 ("drm/nouveau: implement new VM_BIND uAPI&quot...
2023 Jul 25
1
[PATCH drm-misc-next v8 03/12] drm/nouveau: new VM_BIND uapi interfaces
...lar, it needs to > wait on all the waits as well as the previous EXECs on that channel and > then signal the sigs. I know Dave has a patch for this and it's working > quite well in my testing. > > Other than that, everything looks good.? I'm still re-reading all the > NVK patches but they've been working quite well in my testing this week > apart from a perf issue I need to dig into. I'll give a real RB once > we're sure we all agree on the semantics of _count. > > ~Faith > > +? ? ? ?/** > +? ? ? ? * @wait_count: the numb...
2003 Aug 02
0
Re: how l (PR#3614)
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