search for: nvea_ibus_intr

...ea_ibus_priv { > + struct nouveau_ibus base; > +}; > + > +static void > +nvea_ibus_init_priv_ring(struct nvea_ibus_priv *priv) > +{ > + nv_mask(priv, 0x137250, 0x3f, 0); > + > + nv_mask(priv, 0x000200, 0x20, 0); > + udelay(20); usleep_range()? > +static void > +nvea_ibus_intr(struct nouveau_subdev *subdev) > +{ [...] > + /* Acknowledge interrupt */ > + nv_mask(priv, 0x12004c, 0x2, 0x2); > + > + while (--retry >= 0) { > + command = nv_rd32(priv, 0x12004c) & 0x3f; > + if (command == 0) > + break; > + } > + > + if (retry < 0)...

...> + > + nv_mask(priv, 0x000200, 0x20, 0); > + udelay(20); > + nv_mask(priv, 0x000200, 0x20, 0x20); > + > + nv_wr32(priv, 0x12004c, 0x4); > + nv_wr32(priv, 0x122204, 0x2); > + nv_rd32(priv, 0x122204); > +} > + > +static void > +nvea_ibus_intr(struct nouveau_subdev *subdev) > +{ > + struct nvea_ibus_priv *priv = (void *)subdev; > + u32 status0 = nv_rd32(priv, 0x120058); > + s32 retry = 100; > + u32 command; > + > + if (status0 & 0x7) { > + nv_debug(priv, "resett...

...ata; + + data = nv_rd32(priv, 0x137250); + data &= (~0x3f); + nv_wr32(priv, 0x137250, data); + + nv_mask(priv, 0x000200, 0x20, 0); + udelay(20); + nv_mask(priv, 0x000200, 0x20, 0x20); + + nv_wr32(priv, 0x12004c, 0x4); + nv_wr32(priv, 0x122204, 0x2); + nv_rd32(priv, 0x122204); +} + +static void +nvea_ibus_intr(struct nouveau_subdev *subdev) +{ + struct nvea_ibus_priv *priv = (void *)subdev; + u32 status0 = nv_rd32(priv, 0x120058); + s32 retry = 100; + u32 command; + + if (status0 & 0x7) { + nv_debug(priv, "resetting priv ring\n"); + nvea_ibus_init_priv_ring(priv); + } + + /* Acknowledge i...

...id +nvea_ibus_init_priv_ring(struct nvea_ibus_priv *priv) +{ + nv_mask(priv, 0x137250, 0x3f, 0); + + nv_mask(priv, 0x000200, 0x20, 0); + udelay(20); + nv_mask(priv, 0x000200, 0x20, 0x20); + + nv_wr32(priv, 0x12004c, 0x4); + nv_wr32(priv, 0x122204, 0x2); + nv_rd32(priv, 0x122204); +} + +static void +nvea_ibus_intr(struct nouveau_subdev *subdev) +{ + struct nvea_ibus_priv *priv = (void *)subdev; + u32 status0 = nv_rd32(priv, 0x120058); + s32 retry = 100; + u32 command; + + if (status0 & 0x7) { + nv_debug(priv, "resetting priv ring\n"); + nvea_ibus_init_priv_ring(priv); + } + + /* Acknowledge i...

...truct nvea_ibus_priv *priv) >>> +{ >>> + nv_mask(priv, 0x137250, 0x3f, 0); >>> + >>> + nv_mask(priv, 0x000200, 0x20, 0); >>> + udelay(20); >> >> usleep_range()? > > Sure. > >> >>> +static void >>> +nvea_ibus_intr(struct nouveau_subdev *subdev) >>> +{ >> [...] >>> + /* Acknowledge interrupt */ >>> + nv_mask(priv, 0x12004c, 0x2, 0x2); >>> + >>> + while (--retry >= 0) { >>> + command = nv_rd32(priv, 0x12004c) & 0x3f; &gt...

...gt; +static void >> +nvea_ibus_init_priv_ring(struct nvea_ibus_priv *priv) >> +{ >> + nv_mask(priv, 0x137250, 0x3f, 0); >> + >> + nv_mask(priv, 0x000200, 0x20, 0); >> + udelay(20); > > usleep_range()? Sure. > >> +static void >> +nvea_ibus_intr(struct nouveau_subdev *subdev) >> +{ > [...] >> + /* Acknowledge interrupt */ >> + nv_mask(priv, 0x12004c, 0x2, 0x2); >> + >> + while (--retry >= 0) { >> + command = nv_rd32(priv, 0x12004c) & 0x3f; >> + if (comm...

Hi everyone, Here is the second batch of patches to add GK20A support to Nouveau. This time we are adding the actual chip support, and this series brings the driver to a point where a slightly-tweaked Mesa successfully runs shaders and renders triangles on GBM! Many thanks to Thierry Reding and the people on the #nouveau IRC channel for their help without which we would not have reached this

Hello everyone, GK20A is the Kepler-based GPU used in the upcoming Tegra K1 chips. The following patches perform architectural changes to Nouveau that are necessary to support non-PCI GPUs and add initial support for GK20A. Although the support is still very basic and more user-space changes will be needed to make the full graphics stack run on top of it, we were able to successfully open