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Changes from v1 to v2: - Use a macro to replace the hardcode in patch 1/3. This patchset fixes issues about IA32_VMX_MISC MSR emulation, VMCS guest area synchronization about PAGE_FAULT_ERROR_CODE_MASK/PAGE_FAULT_ERROR_CODE_MATCH, and CR0/CR4 emulation. Please help to review and pull. Thanks, Dongxiao Dongxiao Xu (3): nested vmx: emulate IA32_VMX_MISC MSR nested vmx: synchronize page

...ct hvm_function_table * __init start_vmx(void) diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 2e0b79d..1f610eb 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -57,6 +57,9 @@ void nvmx_vcpu_destroy(struct vcpu *v) { struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v); + if ( nvcpu->nv_n1vmcx ) + v->arch.hvm_vmx.vmcs = nvcpu->nv_n1vmcx; + nvmx_purge_vvmcs(v); if ( nvcpu->nv_n2vmcx ) { __vmpclear(virt_to_maddr(nvcpu->nv_n2vmcx)); @@ -65,6 +68,14 @@ void nvmx_vcpu_destroy(struct vcpu *v) }...

Changes from v2 to v3: - Use pfn_to_paddr() to get the address from frame number instead of doing shift directly. - Remove some unnecessary initialization code and add "static" to vmentry_fields and gpdptr_fields. - Enable the VMREAD/VMWRITE bitmap only if nested hvm is enabled. - Use clear_page() to set all 0 to the page instead of memset(). - Use domheap to allocate the

...to gpf; diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index f385c02..d55d60c 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1341,6 +1341,7 @@ static void virtual_vmexit(struct cpu_user_regs *regs) nestedhvm_vcpu_exit_guestmode(v); nvcpu->nv_vmexit_pending = 0; + nvcpu->nv_vmswitch_in_progress = 1; lm_l2 = !!hvm_long_mode_enabled(v); lm_l1 = !!(__get_vvmcs(nvcpu->nv_vvmcx, VM_EXIT_CONTROLS) & @@ -1371,6 +1372,7 @@ static void virtual_vmexit(struct cpu_user_regs *regs) if ( cpu_has_vmx_virtual_intr_d...

...apic_access_address(struct vcpu *v) __vmwrite(APIC_ACCESS_ADDR, (apic_mfn << PAGE_SHIFT)); hvm_unmap_guest_frame(apic_va); } + else + __vmwrite(APIC_ACCESS_ADDR, 0); +} + +static void nvmx_update_virtual_apic_address(struct vcpu *v) +{ + struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v); + u64 vapic_gpfn, vapic_mfn; + u32 ctrl; + void *vapic_va; + + ctrl = __n2_exec_control(v); + if ( ctrl & CPU_BASED_TPR_SHADOW ) + { + vapic_gpfn = __get_vvmcs(nvcpu->nv_vvmcx, VIRTUAL_APIC_PAGE_ADDR) >> PAGE_SHIFT; + vapic_va =...

From: Yang Zhang <yang.z.zhang@Intel.com> The following patches fix the issue that fail to boot L2 guest on APIC-v available machine. The main problem is that with APIC-v, virtual interrupt inject L1 is totally through APIC-v. But if virtual interrupt is arrived when L2 is running, L1 will detect interrupt through vmexit with reason external interrupt. If this happens, we should update

...( nestedhvm_enabled(v->domain) && hvm_funcs.nhvm_vcpu_destroy ) + if ( hvm_funcs.nhvm_vcpu_destroy ) hvm_funcs.nhvm_vcpu_destroy(v); } --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -62,7 +62,7 @@ int nvmx_vcpu_initialise(struct vcpu *v) if ( !nvcpu->nv_n2vmcx ) { gdprintk(XENLOG_ERR, "nest: allocation for shadow vmcs failed\n"); - goto out; + return -ENOMEM; } /* non-root VMREAD/VMWRITE bitmap. */ @@ -75,7 +75,7 @@ int nvmx_vcpu_initialise(struct vcpu *v) if ( !vmread_bitmap ) {...

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

while doing "while xm migrate --live domU localhost;do sleep 1;done" I just got the crash shown below. And it can be reproduced. The guest has 2 vcpus and 512mb, it runs pvops 3.7.9 (XEN) ----[ Xen-4.3.26579-20130219.172714 x86_64 debug=n Not tainted ]---- (XEN) CPU: 14 (XEN) RIP: e008:[<ffff82c4c01dd197>] nvmx_vcpu_destroy+0xb7/0x150 (XEN) RFLAGS: 0000000000010282