Displaying 4 results from an estimated 4 matches for "nvcopy".
2016 Oct 27
1
[PATCH v2 6/7] copy: add maxwell/pascal copy engine classes
...a0b5, 0xa0b5,
> + if (pNv->dev->chipset < 0x110)
> + class = 0xa0b5;
> + else if (pNv->dev->chipset < 0x130)
> + class = 0xb0b5;
> + else
> + class = 0xc0b5;
> +
> + ret = nouveau_object_new(pNv->channel, class, class,
> NULL, 0, &pNv->NvCOPY);
> if (ret)
> return FALSE;
>
2016 Oct 27
0
[PATCH v2 6/7] copy: add maxwell/pascal copy engine classes
...= nouveau_object_new(pNv->channel, 0x0000a0b5, 0xa0b5,
+ if (pNv->dev->chipset < 0x110)
+ class = 0xa0b5;
+ else if (pNv->dev->chipset < 0x130)
+ class = 0xb0b5;
+ else
+ class = 0xc0b5;
+
+ ret = nouveau_object_new(pNv->channel, class, class,
NULL, 0, &pNv->NvCOPY);
if (ret)
return FALSE;
--
2.7.3
2015 Mar 14
1
[PATCH ddx] Add support for VRAM-less devices to the ddx
.../nv_type.h
index e6ab192..c5a2684 100644
--- a/src/nv_type.h
+++ b/src/nv_type.h
@@ -122,6 +122,7 @@ typedef struct _NVRec {
struct nouveau_bo *scratch;
Bool ce_enabled;
+ uint32_t vram_domain;
struct nouveau_object *ce_channel;
struct nouveau_pushbuf *ce_pushbuf;
struct nouveau_object *NvCopy;
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 848ca87..7188230 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -242,7 +242,7 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
if (nouveau_pushbuf_space(push, 512, 0, 0) ||
nouveau_pushbuf_refn (push, &(struct nouveau_pushbuf_re...
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
I believe I've addressed all the feedback from the first time around, and
also made fixes necessary for GM20x based on testing results. I believe
now it should actually work for all GM10x and GM20x. Further, GP10x should
be very easy to add, but without someone to actually test I didn't want to
claim support for it.
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update