Displaying 10 results from an estimated 10 matches for "nvc0legalizessa".
2019 Jul 18
3
[Bug 111167] New: Dividing zero by a uniform in loop header causes segfault in nv50_ir::NVC0LegalizeSSA::handleDIV
https://bugs.freedesktop.org/show_bug.cgi?id=111167
Bug ID: 111167
Summary: Dividing zero by a uniform in loop header causes
segfault in nv50_ir::NVC0LegalizeSSA::handleDIV
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: minor
Priority: medium
Component: Drivers/DRI/nouveau
Assignee: nouveau at lists.freedesktop.org...
2019 Jul 25
9
[Bug 111218] New: Segmentation fault in nv50_ir::NVC0LegalizeSSA::handleDIV when dividing result of textureSize
https://bugs.freedesktop.org/show_bug.cgi?id=111218
Bug ID: 111218
Summary: Segmentation fault in
nv50_ir::NVC0LegalizeSSA::handleDIV when dividing
result of textureSize
Product: Mesa
Version: 19.0
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: major
Priority: medium
Component: Drivers/DRI/nouvea...
2015 Feb 23
2
[Mesa-dev] [PATCH 2/2] nvc0/ir: improve precision of double RCP/RSQ results
...degen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> index 87e75e1..9767566 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> @@ -77,8 +77,9 @@ NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
> bld.setPosition(i, false);
>
> // 1. Take the source and it up.
> - Value *src[2], *dst[2], *def = i->getDef(0);
> - bld.mkSplit(src, 4, i->getSrc(0));
> + Value *input = i->getSrc(0);
> + Value *src[2], *dst[2], *guess...
2017 Aug 12
3
[PATCH] nvc0/ir: propagate immediates to CALL input MOVs
...rs/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index c8f0701572..861d08af24 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -47,8 +47,25 @@ NVC0LegalizeSSA::handleDIV(Instruction *i)
int builtin;
bld.setPosition(i, false);
- bld.mkMovToReg(0, i->getSrc(0));
- bld.mkMovToReg(1, i->getSrc(1));
+
+ // Generate movs to the input regs for the call we want to generate
+ for (int s = 0; i->srcExists(s); ++s) {
+ Instruction *l...
2015 Feb 23
0
[PATCH 2/2] nvc0/ir: improve precision of double RCP/RSQ results
...m/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 87e75e1..9767566 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -77,8 +77,9 @@ NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
bld.setPosition(i, false);
// 1. Take the source and it up.
- Value *src[2], *dst[2], *def = i->getDef(0);
- bld.mkSplit(src, 4, i->getSrc(0));
+ Value *input = i->getSrc(0);
+ Value *src[2], *dst[2], *guess, *def = i->getDef(0);
+ bld.m...
2015 Feb 23
0
[Mesa-dev] [PATCH 2/2] nvc0/ir: improve precision of double RCP/RSQ results
...wering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> index 87e75e1..9767566 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> @@ -77,8 +77,9 @@ NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
>> bld.setPosition(i, false);
>>
>> // 1. Take the source and it up.
>> - Value *src[2], *dst[2], *def = i->getDef(0);
>> - bld.mkSplit(src, 4, i->getSrc(0));
>> + Value *input = i->getSrc(0);
>> + Valu...
2015 Feb 23
2
[PATCH 1/2] nv50/ir: add fp64 support on G200 (NVA0)
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
Untested beyond compiling a few shaders to see if they look like they
might work. nvdisasm agrees with envydis's decoding of these things.
Will definitely get ahold of a G200 to run tests on before pushing this.
.../drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 94 ++++++++++++++++++---
2017 Aug 13
1
[PATCH v2] nvc0/ir: propagate immediates to CALL input MOVs
...rs/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index c8f0701572..7243b1d2e4 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -47,8 +47,25 @@ NVC0LegalizeSSA::handleDIV(Instruction *i)
int builtin;
bld.setPosition(i, false);
- bld.mkMovToReg(0, i->getSrc(0));
- bld.mkMovToReg(1, i->getSrc(1));
+
+ // Generate movs to the input regs for the call we want to generate
+ for (int s = 0; i->srcExists(s); ++s) {
+ Instruction *l...
2017 Aug 12
0
[PATCH] nvc0/ir: propagate immediates to CALL input MOVs
...v50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> index c8f0701572..861d08af24 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> @@ -47,8 +47,25 @@ NVC0LegalizeSSA::handleDIV(Instruction *i)
> int builtin;
>
> bld.setPosition(i, false);
> - bld.mkMovToReg(0, i->getSrc(0));
> - bld.mkMovToReg(1, i->getSrc(1));
> +
> + // Generate movs to the input regs for the call we want to generate
> + for (int s = 0; i->srcE...
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++-
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index dfb093c..e38a3b8 100644
---