search for: nvc0legalizepostra

Displaying 5 results from an estimated 5 matches for "nvc0legalizepostra".

[PATCH 1/2] nvc0/ir: avoid infinite recursion when finding first uses of tex
2014 Aug 30
2
[PATCH 1/2] nvc0/ir: avoid infinite recursion when finding first uses of tex
...ivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 7da9b0b..92f9a15 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -174,15 +174,31 @@ NVC0LegalizePostRA::findOverwritingDefs(const Instruction *texi, } void -NVC0LegalizePostRA::findFirstUses(const Instruction *texi, - const Instruction *insn, - std::list<TexUse> &uses) +NVC0LegalizePostRA::findFirstUses( + const Ins...
[PATCH] nv50/ir: we can't replace 0x0 with zero reg for SHLADD
2017 Apr 29
2
[PATCH] nv50/ir: we can't replace 0x0 with zero reg for SHLADD
...s/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 732e1a93b4..4815d6df07 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -740,7 +740,7 @@ NVC0LegalizePostRA::visit(BasicBlock *bb) next = hi; } - if (i->op != OP_MOV && i->op != OP_PFETCH) + if (i->op != OP_MOV && i->op != OP_PFETCH && i->op != OP_SHLADD) replaceZero(i); } } -- 2.12.2
[PATCH RESEND] nv50/ir: use unordered_set instead of list to keep track of var defs
2014 Dec 02
0
[PATCH RESEND] nv50/ir: use unordered_set instead of list to keep track of var defs
...drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 9c06d04..ab28f3a 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -148,7 +148,7 @@ NVC0LegalizePostRA::findOverwritingDefs(const Instruction *texi, std::list<TexUse> &uses) { while (insn->op == OP_MOV && insn->getDef(0)->equals(insn->getSrc(0))) - insn = insn->getSrc(0)->getUniqueInsn(); + insn = insn->ge...
[PATCH] nv50/ir: we can't replace 0x0 with the zero reg for SHLADD
2017 Apr 29
0
[PATCH] nv50/ir: we can't replace 0x0 with the zero reg for SHLADD
...s/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 732e1a93b4..4815d6df07 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -740,7 +740,7 @@ NVC0LegalizePostRA::visit(BasicBlock *bb) next = hi; } - if (i->op != OP_MOV && i->op != OP_PFETCH) + if (i->op != OP_MOV && i->op != OP_PFETCH && i->op != OP_SHLADD) replaceZero(i); } } -- 2.12.2
[PATCH] nv50/ir: we can't replace 0x0 with zero reg for SHLADD
2017 Apr 29
0
[PATCH] nv50/ir: we can't replace 0x0 with zero reg for SHLADD
...50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp > index 732e1a93b4..4815d6df07 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp > @@ -740,7 +740,7 @@ NVC0LegalizePostRA::visit(BasicBlock *bb) > next = hi; > } > > - if (i->op != OP_MOV && i->op != OP_PFETCH) > + if (i->op != OP_MOV && i->op != OP_PFETCH && i->op != OP_SHLADD) > replaceZero(i); >...