search for: nvc0_bus_oclass

..._ENGINE_PERFMON] = &nve0_perfmon_oclass; > break; > + case 0xea: > + device->cname = "GK20A"; > + device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; > + device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; > + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; As per note on the PTIMER patch, can just switch this to "gk20a_timer_oclass" on the latest code. > + device->oclass[NVDEV_SUBDEV_FB ] = nvea_fb_oclass; > + d...

..., 1 insertion(+) diff --git a/nvkm/engine/device/nve0.c b/nvkm/engine/device/nve0.c index 54ec53bc6252..cdf9147f32a1 100644 --- a/nvkm/engine/device/nve0.c +++ b/nvkm/engine/device/nve0.c @@ -163,6 +163,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; device->oclass[NVDEV_SUBDE...

...ss[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; <<<<<==== device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; The dmesg and Xorg.0.log with the problem captured across a ssh link. # ps fax|grep X 5633 pts/0 S+ 0:00 \_ grep --color=auto X 5160 tty7 Ss+ 0:08 \_ /usr/bin/Xorg -br :0 vt7 -nolisten...

...mp;nv50_mxm_oclass; >> device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; >> device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; >> <<<<<==== >> device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; >> device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; > That's the 0xc3 case... you have a nvce card, not nvc3 -- you would > need to change the NVDEV_SUBDEV_MC line to nvc0_mc_oclass for the 0xce > case. > >> The dmesg and Xorg.0.log wit...

...UBDEV_MXM ] = &nv50_mxm_oclass; > device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; > device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; > <<<<<==== > device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; > device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; That's the 0xc3 case... you have a nvce card, not nvc3 -- you would need to change the NVDEV_SUBDEV_MC line to nvc0_mc_oclass for the 0xce case. > > The dmesg and Xorg.0.log with the problem captured...

...>oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; break; + case 0xea: + device->cname = "GK20A"; + device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nvea_fb_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &nvea_ibus_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV...

...t;oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; + device->oclass[NVDEV_SUBDEV_I...

...gt; device->oclass[NVDEV_SUBDEV_DEVINIT] = >>> &nvc0_devinit_oclass; >>> device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; >>> <<<<<==== >>> device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; >>> device->oclass[NVDEV_SUBDEV_TIMER ] = >>> &nv04_timer_oclass; >> >> That's the 0xc3 case... you have a nvce card, not nvc3 -- you would >> need to change the NVDEV_SUBDEV_MC line to nvc0_mc_oclass for the 0xce >> case. >...

...gt;oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; + device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; + device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; + device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; + device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass; + device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; + device->oclass[NVDEV_SUBDEV_...

...device->cname = "GK20A"; >> + device->oclass[NVDEV_SUBDEV_CLOCK ] = >> &gk20a_clock_oclass; >> device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; >> device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; >> device->oclass[NVDEV_SUBDEV_TIMER ] = >> &gk20a_timer_oclass; >> diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h >> b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h >> index c0fe191c9787..9fed2834f25e 100644 >> --...

...ouveau_device *device) > break; > case 0xea: > device->cname = "GK20A"; > + device->oclass[NVDEV_SUBDEV_CLOCK ] = &gk20a_clock_oclass; > device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; > device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; > device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; > diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h > index c0fe191c9787..9fed2834f25e 100644 > --- a/drivers/gpu/drm/nouveau/core/include/subde...

On 31/12/13 10:36, Ilia Mirkin wrote: > On Tue, Dec 31, 2013 at 5:14 AM, Sid Boyce <sboyce at blueyonder.co.uk> wrote: >> System x86_64 with openSUSE 13.1. >> X.Org version: 1.14.99.905 >> >> openSUSE 12.2 kernels boot successfully into a graphical screen, login to >> KDE4, etc. all normal. >> >> 3.13-rc kernels boot fully with X running but no

...,6 +158,7 @@ nve0_identify(struct nouveau_device *device) break; case 0xea: device->cname = "GK20A"; + device->oclass[NVDEV_SUBDEV_CLOCK ] = &gk20a_clock_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h index c0fe191c9787..9fed2834f25e 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h +++ b/drive...

...MXM ] = &nv50_mxm_oclass; > @@ -161,6 +165,7 @@ nve0_identify(struct nouveau_device *device) > device->oclass[NVDEV_SUBDEV_CLOCK ] = &gk20a_clock_oclass; > device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; > device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; > + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; > device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; > device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; > device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; > @@ -...

...gt;oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; @@ -161,6 +165,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_CLOCK ] = &gk20a_clock_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; + device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; @@ -180,6 +185,7 @@ nve0_identif...

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wrong in terms of integration to your tree, as the main purpose of

Hi everyone, Here is the second batch of patches to add GK20A support to Nouveau. This time we are adding the actual chip support, and this series brings the driver to a point where a slightly-tweaked Mesa successfully runs shaders and renders triangles on GBM! Many thanks to Thierry Reding and the people on the #nouveau IRC channel for their help without which we would not have reached this

Latest patches for GK20A, taking comments received for v3 into account. Changes since v3: - use only pfn_to_page() and page_to_pfn() in GK20A's FB. These functions are present on every arch and the physical address to page frame number conversion is also consistently a shift of PAGE_SHIFT. This part will probably be replaced by something nicer in the future anyway. - fixed a warning on

Hi everyone, Way overdue v2 of the final patches that enable basic GK20A support. Hopefully all the issues raised with v1 have been addressed. Changes since v1: - Use gk20a clock driver by Ben instead of twiddling nv04's - Name new classes after gk20a instead of nvea - Addressed comments about BAR initialization code factorization - Removed non-essential code which only purpose was to avoid