search for: nvbios_rd16

...h, > + u8 idx, struct nvbios_thermal_policies_entry *e) > +{ > + u32 offset; > + > + if (!e || !h || idx > h->ecount) > + return -EINVAL; > + > + offset = h->offset + h->hlen + idx * h->elen; > + e->mode = nvbios_rd08(b, offset); > + e->t0 = nvbios_rd16(b, offset + 0x2); > + e->t1 = nvbios_rd16(b, offset + 0x4); > + e->t2 = nvbios_rd16(b, offset + 0x6); > + e->down_offset = nvbios_rd16(b, offset + 0x12); > + e->up_offset = nvbios_rd16(b, offset + 0x14); > + > + return 0; > +} > -- > 2.14.1 > > _______...

...s_rd08(bios, volt + 0x04); + info->type = NVBIOS_VOLT_GPIO; + info->vidmask = nvbios_rd08(bios, volt + 0x04); + info->entry_based = true; break; case 0x40: - info->type = NVBIOS_VOLT_GPIO; - info->base = nvbios_rd32(bios, volt + 0x04); - info->step = nvbios_rd16(bios, volt + 0x08); - info->vidmask = nvbios_rd08(bios, volt + 0x0b); + info->type = NVBIOS_VOLT_GPIO; + info->base = nvbios_rd32(bios, volt + 0x04); + info->step = nvbios_rd16(bios, volt + 0x08); + info->vidmask = nvbios_rd08(bios, volt + 0x0b); + info...

...m_bios *b, struct nvbios_thermal_policies_header *h, + u8 idx, struct nvbios_thermal_policies_entry *e) +{ + u32 offset; + + if (!e || !h || idx > h->ecount) + return -EINVAL; + + offset = h->offset + h->hlen + idx * h->elen; + e->mode = nvbios_rd08(b, offset); + e->t0 = nvbios_rd16(b, offset + 0x2); + e->t1 = nvbios_rd16(b, offset + 0x4); + e->t2 = nvbios_rd16(b, offset + 0x6); + e->down_offset = nvbios_rd16(b, offset + 0x12); + e->up_offset = nvbios_rd16(b, offset + 0x14); + + return 0; +} -- 2.14.1

...Herbst + */ +#include <subdev/bios.h> +#include <subdev/bios/bit.h> +#include <subdev/bios/baseclock.h> + +static u16 +nvbios_baseclock_offset(struct nvkm_bios *b) +{ + struct bit_entry bit_P; + + if (!bit_entry(b, 'P', &bit_P)) { + if (bit_P.version == 2) + return nvbios_rd16(b, bit_P.offset + 0x38); + } + + return 0x0000; +} + +int +nvbios_baseclock_parse(struct nvkm_bios *b, struct nvbios_baseclk_header *h) +{ + if (!h) + return -EINVAL; + + h->offset = nvbios_baseclock_offset(b); + if (!h->offset) + return -ENODEV; + + h->version = nvbios_rd08(b, h->off...

On a very few GPUs with the voltage table version 0x50 we have to read out the VIDs out of the entries of the table, where all the other gpus are either PWM based or get a base and a step voltage out of the table header. Currently nouveau tried to autodetect this and actually doesn't parse the entries. This Series adds two things: 1. It parses the entries 2. It decides upon a field in the

This series fixes most of the issues regarding volting on GPUs with any form of GPU Boost inside their vbios, which is mainly Kepler and newer, but we find some boosting related tables in Fermi vbios' already In the end reclocking should work on most Kepler cards without any issues Karol Herbst (19): bios/volt: handle voltage table version 0x50 with 0ed header volt: properly detect entry

...*len, u8 *cnt) u16 dcb, extdev = 0; dcb = dcb_table(bios, &dcb_ver, &dcb_hdr, &dcb_cnt, &dcb_len); - if (!dcb || (dcb_ver != 0x30 && dcb_ver != 0x40)) + if (!dcb || (dcb_ver != 0x30 && dcb_ver != 0x40 && dcb_ver != 0x41)) return 0x0000; extdev = nvbios_rd16(bios, dcb + 18); -- 2.7.1

.../drm/nouveau/nvkm/subdev/bios/perf.c @@ -213,3 +213,17 @@ nvbios_perf_fan_parse(struct nvkm_bios *bios, return 0; } + +u16 +nvbios_perf_script_unk1c(struct nvkm_bios *bios) +{ + struct bit_entry bit_P; + + if (!bit_entry(bios, 'P', &bit_P)) { + if (bit_P.version == 2) { + return nvbios_rd16(bios, bit_P.offset + 0x1c); + } + } + + return 0x0000; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index eebd20b..def119c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subd...

.../drm/nouveau/nvkm/subdev/bios/perf.c @@ -213,3 +213,17 @@ nvbios_perf_fan_parse(struct nvkm_bios *bios, return 0; } + +u16 +nvbios_perf_script_unk1c(struct nvkm_bios *bios) +{ + struct bit_entry bit_P; + + if (!bit_entry(bios, 'P', &bit_P)) { + if (bit_P.version == 2) { + return nvbios_rd16(bios, bit_P.offset + 0x1c); + } + } + + return 0x0000; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index eebd20b..def119c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subd...

...eau/nvkm/subdev/bios/volt.c b/drm/nouveau/nvkm/subdev/bios/volt.c index a7797a9e..7143ea46 100644 --- a/drm/nouveau/nvkm/subdev/bios/volt.c +++ b/drm/nouveau/nvkm/subdev/bios/volt.c @@ -93,9 +93,9 @@ nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, info->step = nvbios_rd16(bios, volt + 0x08); info->vidmask = nvbios_rd08(bios, volt + 0x0b); info->ranged = true; /* XXX: find the flag byte */ - /*XXX*/ - info->min = 0; - info->max = info->base; + info->min = min(info->base, + info->base + info->step * info->vid...

.../drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c index c306835..7112992 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c @@ -135,6 +135,7 @@ nvbios_perfEp(struct nvkm_bios *bios, int idx, break; case 0x30: info->script = nvbios_rd16(bios, perf + 0x02); + /* fall through */ case 0x35: info->fanspeed = nvbios_rd08(bios, perf + 0x06); info->voltage = nvbios_rd08(bios, perf + 0x07); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c index e6e804c..bda6cc9 10...

Adds Nouveau controlled thermal throttling for Kepler+ GPUs. With this I feel safe enough to add support for Maxwell2 reclocking later on (still hidden behind a switch, but we can be fairly sure to not overheat hardware if a user isn't carefull enough) Contains all patches from my clk update series, but I thought it makes sense to include those in this series as well for completness. Please

...s/iccsense.h> + +static u16 +nvbios_iccsense_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, + u8 *len) +{ + struct bit_entry bit_P; + u16 iccsense; + + if (bit_entry(bios, 'P', &bit_P) || bit_P.version != 2 || + bit_P.length < 0x2c) + return 0; + + iccsense = nvbios_rd16(bios, bit_P.offset + 0x28); + if (!iccsense) + return 0; + + *ver = nvbios_rd08(bios, iccsense + 0); + switch (*ver) { + case 0x10: + case 0x20: + *hdr = nvbios_rd08(bios, iccsense + 1); + *len = nvbios_rd08(bios, iccsense + 2); + *cnt = nvbios_rd08(bios, iccsense + 3); + return iccsense; + de...

This series fixes most of the issues regarding volting on GPUs with any form of GPU Boost inside their vbios, which is mainly Kepler and newer, but we find some boosting related tables in Fermi vbios' already In the end reclocking should work on most Kepler cards without any issues v2: boost_mode can now be changed at runtime minor fixups Karol Herbst (22): bios/volt: handle voltage

.../drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c index c306835..7112992 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c @@ -135,6 +135,7 @@ nvbios_perfEp(struct nvkm_bios *bios, int idx, break; case 0x30: info->script = nvbios_rd16(bios, perf + 0x02); + /* fall through */ case 0x35: info->fanspeed = nvbios_rd08(bios, perf + 0x06); info->voltage = nvbios_rd08(bios, perf + 0x07); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c index e6e804c..62ec3ee 10...

...t;resistor_count = 0; break; }; + + for (r = 0; r < rail->resistor_count; ++r) { + rail->resistors[r].mohm = nvbios_rd08(bios, entry + res_start + r * 2); + rail->resistors[r].enabled = !(nvbios_rd08(bios, entry + res_start + r * 2 + 1) & 0x40); + } + rail->config = nvbios_rd16(bios, entry + res_start + rail->resistor_count * 2); } return 0; diff --git a/drm/nouveau/nvkm/subdev/iccsense/base.c b/drm/nouveau/nvkm/subdev/iccsense/base.c index 41bd5d0..658355f 100644 --- a/drm/nouveau/nvkm/subdev/iccsense/base.c +++ b/drm/nouveau/nvkm/subdev/iccsense/base.c @@ -96,6...

Last update here: https://lists.freedesktop.org/archives/nouveau/2017-September/028848.html Basically big cleanup, reordering, simplifications and some renaming to make the code easier to read and to review. I also moved some bugfixes to the front so they can be merged prior the other patches. There was also a bug related to the therm daemon triggering a pstate change leading to PMU lockups,

This series contains a lot of groundwork to finally fix reclocking issues on Kepler+ gpus. There shouldn't be any functional changes with the first patch being the only exception (fixes some voltage table parsing issues with of few kepler gpus) The most interessting thing is the tool in the last patch, which can be ran alongside the nvidia driver to test nouveaus volting code and print the

...ios/perf.c > index c306835..7112992 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c > @@ -135,6 +135,7 @@ nvbios_perfEp(struct nvkm_bios *bios, int idx, > break; > case 0x30: > info->script = nvbios_rd16(bios, perf + 0x02); > + /* fall through */ > case 0x35: > info->fanspeed = nvbios_rd08(bios, perf + 0x06); > info->voltage = nvbios_rd08(bios, perf + 0x07); > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll...

Just wanted to post updated versions of my last series/patches. Reviews welcomed. It would be also nice if we agree on features I should focus upstreaming, so that this work can be better splitted or reordered. Sadly most of my patches depend on the rather big clk subdev rework and I think those patches shows best, why I think this rework is actually needed and makes things much easier to add