Displaying 10 results from an estimated 10 matches for "nvbios_pll_parse".
2020 Aug 27
0
[PATCH] drm/nouveau: remove redundant check
...<trix at redhat.com>
clang static analysis flags this problem
hw.c:271:12: warning: The left operand of '>=' is a
garbage value
if (pv.M1 >= pll_lim.vco1.min_m ...
~~~~~ ^
This is mostly not a problem because an early check in
nouveau_hw_fix_bad_vpll()
if (nvbios_pll_parse(bios, pll, &pll_lim))
return;
nouveau_hw_get_pllvals(dev, pll, &pv);
shadows a similar check in nouveau_hw_get_pllvals()
ret = nvbios_pll_parse(bios, plltype, &pll_lim);
if (ret || !(reg1 = pll_lim.reg))
return -ENOENT;
Since the first check is redundant, remove it and
check t...
2017 Dec 02
0
nouveau: refcount_t splat on 4.15-rc1 on nv50
...: 0000000225232000 CR4: 00000000000006f0
[ 9.909417] Call Trace:
[ 9.912106] nv50_instobj_acquire+0x123/0x1c0 [nouveau]
[ 9.917565] ? nvbios_rd08+0x1b/0x70 [nouveau]
[ 9.922239] nvkm_instobj_new+0x1e3/0x520 [nouveau]
[ 9.927353] ? nvbios_rd08+0x1b/0x70 [nouveau]
[ 9.932017] ? nvbios_pll_parse+0x8d7/0xcf0 [nouveau]
[ 9.937218] ? kmem_cache_alloc+0x1f0/0x2d0
[ 9.941624] nvkm_memory_new+0x4b/0xc0 [nouveau]
[ 9.946461] ? nvkm_longopt+0x17/0x60 [nouveau]
[ 9.951208] gf100_fb_oneinit+0x7b/0x1c0 [nouveau]
[ 9.956218] nvkm_fb_oneinit+0x89/0x2e0 [nouveau]
[ 9.961144] nvkm...
2017 Jan 10
0
[bug report] drm/nouveau/devinit: move simple pll setting routines to devinit
...vkm_subdev *subdev = &init->subdev;
38 struct nvkm_device *device = subdev->device;
39 struct nvkm_bios *bios = device->bios;
40 struct nvbios_pll info;
41 int N1, M1, N2, M2, P;
42 int ret;
43
44 ret = nvbios_pll_parse(bios, type, &info);
45 if (ret) {
46 nvkm_error(subdev, "failed to retrieve pll data, %d\n", ret);
47 return ret;
48 }
49
50 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &...
2014 Aug 21
0
[PATCH 2/7] clock/nva3: Set PLL refclk
...we can get a within [-2, 3) MHz of a divider, we'll disable the
+ * PLL and use the divider instead. */
+ clk_khz = nva3_clk_info(clock, clk, khz, info);
+ diff = khz - clk_khz;
+ if (!pll || (diff >= -2000 && diff < 3000)) {
+ return clk_khz;
+ }
+
+ /* Try with PLL */
ret = nvbios_pll_parse(bios, pll, &limits);
if (ret)
return ret;
- limits.refclk = read_clk(priv, clk - 0x10, true);
- if (!limits.refclk)
+ clk_khz = nva3_clk_info(clock, clk - 0x10, limits.refclk, info);
+ if (clk_khz != limits.refclk)
return -EINVAL;
ret = nva3_pll_calc(nv_subdev(priv), &limits,...
2020 May 05
2
problems with NVS310
...0000000576c0a004
CR4: 00000000000606f0
[Fri May? 1 09:07:21 2020] Call Trace:
[Fri May? 1 09:07:21 2020]? ? bit_entry+0xa1/0xc0 [nouveau]
[Fri May? 1 09:07:21 2020]? ? pll_limits_table+0x100/0x190 [nouveau]
[Fri May? 1 09:07:21 2020]? ? nvbios_rd08+0x20/0x40 [nouveau]
[Fri May? 1 09:07:21 2020]? ? nvbios_pll_parse+0x725/0xb60 [nouveau]
[Fri May? 1 09:07:21 2020]? nv50_disp_super_2_2+0x70/0x4a0 [nouveau]
[Fri May? 1 09:07:21 2020]? gf119_disp_super+0x17e/0x2d0 [nouveau]
[Fri May? 1 09:07:21 2020]? process_one_work+0x1a7/0x3a0
[Fri May? 1 09:07:21 2020]? worker_thread+0x30/0x390
[Fri May? 1 09:07:21 2020]? ? c...
2013 Nov 16
0
[PATCH] drm/nouveau/clk: Implement reclocking for NVAA/NVAC
...rce %d 0x%08x\n", src, mast);
+ return 0;
+}
+
+static u32
+calc_pll(struct nvaa_clock_priv *priv, u32 reg,
+ u32 clock, int *N, int *M, int *P)
+{
+ struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvbios_pll pll;
+ struct nouveau_clock *clk = &priv->base;
+ int ret;
+
+ ret = nvbios_pll_parse(bios, reg, &pll);
+ if (ret)
+ return 0;
+
+ pll.vco2.max_freq = 0;
+ pll.refclk = clk->read(clk, nv_clk_src_href);
+ if (!pll.refclk)
+ return 0;
+
+ return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P);
+}
+
+static inline u32
+calc_P(u32 src, u32 target, int *div)...
2013 Nov 17
0
[PATCH] drm/nouveau/clk: Implement reclocking for NVAA/NVAC
...rce %d 0x%08x\n", src, mast);
+ return 0;
+}
+
+static u32
+calc_pll(struct nvaa_clock_priv *priv, u32 reg,
+ u32 clock, int *N, int *M, int *P)
+{
+ struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvbios_pll pll;
+ struct nouveau_clock *clk = &priv->base;
+ int ret;
+
+ ret = nvbios_pll_parse(bios, reg, &pll);
+ if (ret)
+ return 0;
+
+ pll.vco2.max_freq = 0;
+ pll.refclk = clk->read(clk, nv_clk_src_href);
+ if (!pll.refclk)
+ return 0;
+
+ return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P);
+}
+
+static inline u32
+calc_P(u32 src, u32 target, int *div)...
2013 Nov 09
2
[PATCH] drm/nouveau/clk: Initial implementation for reclocking NVAA/NVAC
Reclocking of NVAA/NVAC is substantially different from NV50+, enough to justify a separate clock implementation. This code is a forward-port of reclocking code that has been sitting in a branch for a while, and has been tested on my NVAC. Traces show no significant reasons why this shouldn't work on NVAA, but testers are always welcome. And since these are IGPs without dedicated RAM to
2020 May 05
2
problems with NVS310
I have a Nvidia NVS310 installed in my Linux computer for a few years.
It works well with the Nvidia driver, and not so well with the Linux
nouveau driver. The Nvidia NVS310 has never worked well with Linux. In
the beginning (many years ago) I decided to install Nvidia proprietary
drivers, but every kernel upgrade would require an additional effort to
have the driver working. That was enough
2014 Aug 21
9
NVA3 clock tree improvements
Following a series of patches to improve nouveaus clock tree parsing. Reclocking these engines (all but memory) is pretty stable on the cards I've tested. Please review and merge when approved.
These patches do not solve the problem that core/shader engine doesn't like to be clocked up too far without fb following, with visible corruption as a result. I suspect this problem is unrelated