Displaying 11 results from an estimated 11 matches for "nvaa_domains".
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nva3_domain
2013 Dec 06
2
Regression: drm/nouveau/clk: implement power state and engine clock control in core (7c856522069755ab9d163a24ac332cd3cb35fe30) breaks GeForce 9400 on Intel Mac Mini Model November 2010 model
...pu/drm/nouveau/core/subdev/clock/nvaa.c:847:1: error: redefinition of 'nvaa_clock_tidy'
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:402:1: note: previous definition of 'nvaa_clock_tidy' was here
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:852:1: error: redefinition of 'nvaa_domains'
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:407:1: note: previous definition of 'nvaa_domains' was here
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:862:1: error: redefinition of 'nvaa_clock_ctor'
drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:417:1: note: previous d...
2014 May 16
2
[PATCH] clk: allow config option to enable reclocking
...lock/nvaa.c
index 7a723b4..6a65fc9 100644
--- a/nvkm/subdev/clock/nvaa.c
+++ b/nvkm/subdev/clock/nvaa.c
@@ -421,7 +421,8 @@ nvaa_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nvaa_clock_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, &priv);
+ ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, true,
+ &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
diff --git a/nvkm/subdev/clock/nvc0.c b/nvkm/subdev/clock/nvc0.c
index c310572..dbf8517 100644
--- a/nvkm/subdev/clock/nvc0.c
+++ b/nvkm/...
2013 Dec 06
0
Regression: drm/nouveau/clk: implement power state and engine clock control in core (7c856522069755ab9d163a24ac332cd3cb35fe30) breaks GeForce 9400 on Intel Mac Mini Model November 2010 model
...veau/core/subdev/clock/nvaa.c:847:1: error: redefinition of 'nvaa_clock_tidy'
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:402:1: note: previous definition of 'nvaa_clock_tidy' was here
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:852:1: error: redefinition of 'nvaa_domains'
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:407:1: note: previous definition of 'nvaa_domains' was here
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:862:1: error: redefinition of 'nvaa_clock_ctor'
> drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c:417:1: n...
2014 May 18
1
[PATCH 1/2] fb: default NvMemExec to on, turning it off is used for debugging only
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
Hope I understood you correctly wrt the mem exec stuff.
nvkm/subdev/fb/ramnv50.c | 2 +-
nvkm/subdev/fb/ramnva3.c | 2 +-
nvkm/subdev/fb/ramnvc0.c | 2 +-
nvkm/subdev/fb/ramnve0.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/nvkm/subdev/fb/ramnv50.c b/nvkm/subdev/fb/ramnv50.c
index ef91b6e..e5d12c2 100644
2014 May 17
0
[PATCH] clk: allow config option to enable reclocking
...a/nvkm/subdev/clock/nvaa.c
> +++ b/nvkm/subdev/clock/nvaa.c
> @@ -421,7 +421,8 @@ nvaa_clock_ctor(struct nouveau_object *parent, struct
nouveau_object *engine,
> struct nvaa_clock_priv *priv;
> int ret;
>
> - ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains,
&priv);
> + ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains,
true,
> + &priv);
> *pobject = nv_object(priv);
> if (ret)
> return ret;
> diff --git a/nvkm/subdev/clock/nvc0.c b/nvkm/subd...
2013 Nov 16
0
[PATCH] drm/nouveau/clk: Implement reclocking for NVAA/NVAC
...s->domains,
+ &priv);
+ *pobject = nv_object(priv);
+ if (ret)
+ return ret;
+
+ priv->base.read = nvaa_clock_read;
+ priv->base.calc = nvaa_clock_calc;
+ priv->base.prog = nvaa_clock_prog;
+ priv->base.tidy = nvaa_clock_tidy;
+ return 0;
+}
+
+static struct nouveau_clocks
+nvaa_domains[] = {
+ { nv_clk_src_crystal, 0xff },
+ { nv_clk_src_href , 0xff },
+ { nv_clk_src_core , 0xff, 0, "core", 1000 },
+ { nv_clk_src_shader , 0xff, 0, "shader", 1000 },
+ { nv_clk_src_vdec , 0xff, 0, "vdec", 1000 },
+ { nv_clk_src_max }
+};
+
+struct nouveau_oclass...
2013 Nov 17
0
[PATCH] drm/nouveau/clk: Implement reclocking for NVAA/NVAC
...s->domains,
+ &priv);
+ *pobject = nv_object(priv);
+ if (ret)
+ return ret;
+
+ priv->base.read = nvaa_clock_read;
+ priv->base.calc = nvaa_clock_calc;
+ priv->base.prog = nvaa_clock_prog;
+ priv->base.tidy = nvaa_clock_tidy;
+ return 0;
+}
+
+static struct nouveau_clocks
+nvaa_domains[] = {
+ { nv_clk_src_crystal, 0xff },
+ { nv_clk_src_href , 0xff },
+ { nv_clk_src_core , 0xff, 0, "core", 1000 },
+ { nv_clk_src_shader , 0xff, 0, "shader", 1000 },
+ { nv_clk_src_vdec , 0xff, 0, "vdec", 1000 },
+ { nv_clk_src_max }
+};
+
+struct nouveau_oclass...
2013 Nov 09
2
[PATCH] drm/nouveau/clk: Initial implementation for reclocking NVAA/NVAC
Reclocking of NVAA/NVAC is substantially different from NV50+, enough to justify a separate clock implementation. This code is a forward-port of reclocking code that has been sitting in a branch for a while, and has been tested on my NVAC. Traces show no significant reasons why this shouldn't work on NVAA, but testers are always welcome. And since these are IGPs without dedicated RAM to
2014 Jul 26
5
[PATCH v2 0/3] drm/gk20a: support for reclocking
Second version of the gk20a clock patches. I have tried to keep the therm and
volt devices mandatory in the clock driver, but unfortunately they are too tied
to bios to allow this, at least for the moment. Consequently this version is
mostly a port of the first version to Ben's tree.
Ben, please let me know what I have done wrong in terms of integration to your
tree, as the main purpose of
2013 Dec 06
2
Regression: drm/nouveau/clk: implement power state and engine clock control in core (7c856522069755ab9d163a24ac332cd3cb35fe30) breaks GeForce 9400 on Intel Mac Mini Model November 2010 model
Hello everyone,
the current git HEAD of Linus Torvalds tree breaks Nouveau on my Mac Mini
Model 2010. I get variation of the following kernel panic when booting.
(gateway) [~] nc -u -l -p 6666
[ 3.796018] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[ 3.796100] ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
[ 3.796304] ata1.00: ATA-7: INTEL SSDSA2M160G2GC, 2CV102HA, max
2014 Jul 10
10
[PATCH 0/3] drm/gk20a: support for reclocking
This series adds support for reclocking on GK20A. The first two patches touch
the clock subsystem to allow GK20A to operate, by making the presence of the
thermal and voltage devices optional, and allowing pstates to be provided
directly instead of being probed using the BIOS (which Tegra does not have).
The last patch adds the GK20A clock device. Arguably the clock can be seen as a
stripped-down