Displaying 5 results from an estimated 5 matches for "nva3_ram_calc".
2014 Sep 29
18
Implement reclocking for DDR2, DDR3, GDDR3
Following a series of patches that implement memory reclocking for NVA3/5/8 with
DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics
cards, but I expect reclocking now to work on many more.
Testers can pick up these patches and test it by enabling pstate
(nouveau.pstate=1). They should then be able to change clocks by writing to
/sys/class/drm/card0/device/pstate. Correct
2014 Sep 12
6
NVA3: Small misc mem reclocking fixes
Patch 1 fixes nva3 bailing due to not finding the right ramcfg
Patch 2 is a resend rebased on 3.17.0-rc4 for setting the vblank period
Patch 3-5 handle writes to per-partition registers, for which NVA3 does not
have special broadcast regs available.
Patch 6 removes local structs from NVA3 reclocking in favour of the already
existing "ram->base." variables, like in NVE0
As always,
2014 Sep 29
0
[PATCH 2/7] fb/ramnva3: Link training for DDR3
...1111e0 = nv_rd32(pfb, 0x1111e0);
+ train->r_111400 = nv_rd32(pfb, 0x111400);
+
+ return 0;
+}
+
+void
+nva3_link_train_fini(struct nouveau_fb *pfb)
+{
+ struct nva3_ram *ram = (void *)pfb->ram;
+
+ if (ram->ltrain.mem)
+ pfb->ram->put(pfb, &ram->ltrain.mem);
+}
+
static int
nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
{
@@ -90,6 +361,9 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
next->freq = freq;
ram->base.next = next;
+ if (ram->ltrain.state == NVA3_TRAIN_ONCE)
+ nva3_link_train(pfb);
+
/* lookup memory config data relevant to the target frequency */...
2014 Aug 21
0
[PATCH 2/7] clock/nva3: Set PLL refclk
...3_clock_info *);
#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
index 8076fb1..686e0d6 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
@@ -123,7 +123,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
timing.data = 0;
}
- ret = nva3_clock_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
+ ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
if (ret < 0) {
nv_error(pfb, "failed mclk calculation\n");
return re...
2014 Aug 21
9
NVA3 clock tree improvements
Following a series of patches to improve nouveaus clock tree parsing. Reclocking these engines (all but memory) is pretty stable on the cards I've tested. Please review and merge when approved.
These patches do not solve the problem that core/shader engine doesn't like to be clocked up too far without fb following, with visible corruption as a result. I suspect this problem is unrelated