search for: nva3_pll_calc

...a lookup table for the P coefficient which I could >> not find in the NVE0 driver, >> - Some registers that NVE0 expects to find are not present on GK20A (e.g. >> 0x137120 and 0x137140), >> - Calculation of MNP is done differently from what is performed in >> nva3_pll_calc(), and it might be interesting to compare the two methods, >> - All the same, the programming sequence is done differently in the ChromeOS >> driver and NVE0 could possibly benefit from it (?) >> >> It would be interesting to try and merge both, but for now I prefer to ha...

.../drm/nouveau/core/subdev/clock/nva3.c @@ -66,6 +66,24 @@ nva3_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq) return ret; } +int +nva3_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info, + int clk, struct nouveau_pll_vals *pv) +{ + int ret, N, M, P; + + ret = nva3_pll_calc(clock, info, clk, &N, NULL, &M, &P); + + if (ret > 0) { + pv->refclk = info->refclk; + pv->N1 = N; + pv->M1 = M; + pv->log2P = P; + } + return ret; +} + + static int nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_o...

...he ChromeOS driver uses a lookup table for the P coefficient which I could > not find in the NVE0 driver, > - Some registers that NVE0 expects to find are not present on GK20A (e.g. > 0x137120 and 0x137140), > - Calculation of MNP is done differently from what is performed in > nva3_pll_calc(), and it might be interesting to compare the two methods, > - All the same, the programming sequence is done differently in the ChromeOS > driver and NVE0 could possibly benefit from it (?) > > It would be interesting to try and merge both, but for now I prefer to have the > two...

...coefficient which I could > >> not find in the NVE0 driver, > >> - Some registers that NVE0 expects to find are not present on GK20A (e.g. > >> 0x137120 and 0x137140), > >> - Calculation of MNP is done differently from what is performed in > >> nva3_pll_calc(), and it might be interesting to compare the two methods, > >> - All the same, the programming sequence is done differently in the ChromeOS > >> driver and NVE0 could possibly benefit from it (?) > >> > >> It would be interesting to try and merge both, but fo...

...ient which I >>> could >>> not find in the NVE0 driver, >>> - Some registers that NVE0 expects to find are not present on GK20A (e.g. >>> 0x137120 and 0x137140), >>> - Calculation of MNP is done differently from what is performed in >>> nva3_pll_calc(), and it might be interesting to compare the two >>> methods, >>> - All the same, the programming sequence is done differently in the >>> ChromeOS >>> driver and NVE0 could possibly benefit from it (?) >>> >>> It would be interesting to try...

...ChromeOS driver uses a lookup table for the P coefficient which I could > not find in the NVE0 driver, > - Some registers that NVE0 expects to find are not present on GK20A (e.g. > 0x137120 and 0x137140), > - Calculation of MNP is done differently from what is performed in > nva3_pll_calc(), and it might be interesting to compare the two methods, > - All the same, the programming sequence is done differently in the ChromeOS > driver and NVE0 could possibly benefit from it (?) > > It would be interesting to try and merge both, but for now I prefer to have the > two...

...ssumption (mainly inherited from code that appeared in xf86-video-nv) that it was always a straight division. > - Some registers that NVE0 expects to find are not present on GK20A (e.g. > 0x137120 and 0x137140), > - Calculation of MNP is done differently from what is performed in > nva3_pll_calc(), and it might be interesting to compare the two methods, > - All the same, the programming sequence is done differently in the ChromeOS > driver and NVE0 could possibly benefit from it (?) > > It would be interesting to try and merge both, but for now I prefer to have the > two c...

...al reasons for this: - The ChromeOS driver uses a lookup table for the P coefficient which I could not find in the NVE0 driver, - Some registers that NVE0 expects to find are not present on GK20A (e.g. 0x137120 and 0x137140), - Calculation of MNP is done differently from what is performed in nva3_pll_calc(), and it might be interesting to compare the two methods, - All the same, the programming sequence is done differently in the ChromeOS driver and NVE0 could possibly benefit from it (?) It would be interesting to try and merge both, but for now I prefer to have the two coexisting to ensure prop...

.../* Try with PLL */ ret = nvbios_pll_parse(bios, pll, &limits); if (ret) return ret; - limits.refclk = read_clk(priv, clk - 0x10, true); - if (!limits.refclk) + clk_khz = nva3_clk_info(clock, clk - 0x10, limits.refclk, info); + if (clk_khz != limits.refclk) return -EINVAL; ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P); if (ret >= 0) { - info->clk = nv_rd32(priv, 0x4120 + (clk * 4)); info->pll = (P << 16) | (N << 8) | M; } @@ -232,7 +251,7 @@ static int calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cst...

...rmation in our docs. Let me ask the right people so we can get to the bottom of this. > >> - Some registers that NVE0 expects to find are not present on GK20A (e.g. >> 0x137120 and 0x137140), >> - Calculation of MNP is done differently from what is performed in >> nva3_pll_calc(), and it might be interesting to compare the two methods, >> - All the same, the programming sequence is done differently in the ChromeOS >> driver and NVE0 could possibly benefit from it (?) >> >> It would be interesting to try and merge both, but for now I prefer to ha...

Following a series of patches to improve nouveaus clock tree parsing. Reclocking these engines (all but memory) is pretty stable on the cards I've tested. Please review and merge when approved. These patches do not solve the problem that core/shader engine doesn't like to be clocked up too far without fb following, with visible corruption as a result. I suspect this problem is unrelated