search for: nv_wr32

...device *dev, int i, uint32_t addr, + uint32_t size, uint32_t pitch) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t limit = max(1u, addr + size) - 1; + + if (pitch) { + if (dev_priv->card_type >= NV_20) + addr |= 1; + else + addr |= 1 << 31; + } + + nv_wr32(dev, NV10_PFB_TLIMIT(i), limit); + nv_wr32(dev, NV10_PFB_TSIZE(i), pitch); + nv_wr32(dev, NV10_PFB_TILE(i), addr); +} + int nv10_fb_init(struct drm_device *dev) { - uint32_t fb_bar_size; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_fb_engine *pfb = &dev_priv...

...V40_PFIFO_CACHE1_METHOD(ptr)); + data = nv_rd32(priv, NV40_PFIFO_CACHE1_DATA(ptr)); + } + + if (!nv04_fifo_swmthd(priv, chid, mthd, data)) { + nv_error(priv, + "CACHE_ERROR - Ch %d/%d Mthd 0x%04x Data 0x%08x\n", + chid, (mthd >> 13) & 7, mthd & 0x1ffc, data); + } + + nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0); + nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); + + nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, + nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) & ~1); + nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); + nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, + nv_rd32(p...

...ct drm_device *dev, int display, const char *name) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + uint32_t trap[6]; + int i, ch; + uint32_t idx = nv_rd32(dev, 0x100c90); + if (idx & 0x80000000) { + idx &= 0xffffff; + if (display) { + for (i = 0; i < 6; i++) { + nv_wr32(dev, 0x100c90, idx | i << 24); + trap[i] = nv_rd32(dev, 0x100c94); + } + for (ch = 0; ch < dev_priv->engine.fifo.channels; ch++) { + struct nouveau_channel *chan = dev_priv->fifos[ch]; + + if (!chan || !chan->ramin) + continue; + + if (trap[1] == chan->ramin...

This will fix races between generated ctxprogs and interrupt handler. Signed-off-by: Marcin Ko?cielnicki <koriakin at 0x04.net> --- drivers/gpu/drm/nouveau/nv50_grctx.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nv50_grctx.c b/drivers/gpu/drm/nouveau/nv50_grctx.c index d105fcd..9f909ab 100644 ---

...ev; u32 crtc0 = nv_rd32(priv, 0x600100); u32 crtc1 = nv_rd32(priv, 0x602100); + u32 pvideo; if (crtc0 & 0x00000001) { nouveau_event_trigger(priv->base.vblank, 0); @@ -69,6 +70,14 @@ nv04_disp_intr(struct nouveau_subdev *subdev) nouveau_event_trigger(priv->base.vblank, 1); nv_wr32(priv, 0x602100, 0x00000001); } + + if (nv_device(priv)->chipset >= 0x10 && + nv_device(priv)->chipset <= 0x40) { + pvideo = nv_rd32(priv, 0x8100); + if (pvideo & ~0x11) + nv_info(priv, "PVIDEO intr: %08x\n", pvideo); + nv_wr32(priv, 0x8100, pvideo); + }...

...ore/engine/graph/nv50.c index 2c7809e..a36adcd 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c @@ -991,10 +991,10 @@ nv50_graph_init(struct nouveau_object *object) /* zero out zcull regions */ for (i = 0; i < 8; i++) { - nv_wr32(priv, 0x402c20 + (i * 8), 0x00000000); - nv_wr32(priv, 0x402c24 + (i * 8), 0x00000000); - nv_wr32(priv, 0x402c28 + (i * 8), 0x00000000); - nv_wr32(priv, 0x402c2c + (i * 8), 0x00000000); + nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000); + nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000); + n...

...scrubbing timeout\n"); + return -ETIMEDOUT; + } else { + nv_mask(pmc, 0x00000200, 0x2000, 0x00000000); + return 0; + } +} +static void +gk20a_pmu_enable_irq(struct gk20a_pmu_priv *priv, struct nvkm_mc *pmc, bool enable) +{ + if (enable) { + nv_debug(priv, "enable pmu irq\n"); + nv_wr32(priv, 0x0010a010, 0xff); + nv_mask(pmc, 0x00000640, 0x1000000, 0x1000000); + nv_mask(pmc, 0x00000644, 0x1000000, 0x1000000); + } else { + nv_debug(priv, "disable pmu irq\n"); + nv_mask(pmc, 0x00000640, 0x1000000, 0x00000000); + nv_mask(pmc, 0x00000644, 0x1000000, 0x00000000); + nv_w...

Otherwise none of the format checks pass, since the width was still in 16.16 encoding. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- This must have been some sort of last-second cleanup I made and forgot to test, because with this code, there's no way it could ever have worked... drivers/gpu/drm/nouveau/dispnv04/overlay.c | 17 +++++++++-------- 1 file changed, 9

...struct nv84_bsp_priv *priv = (void *)subdev; > + u32 intr, unk104, unk10c, chan; > + > + unk104 = nv_rd32(priv, 0x103d04); > + intr = nv_rd32(priv, 0x103c20); > + chan = nv_rd32(priv, 0x103c28); > + unk10c = nv_rd32(priv, 0x103d0c); > + nv_wr32(priv, 0x103c20, intr); > + intr = nv_rd32(priv, 0x103c20); > + if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) { > + nv_debug(priv, "Enabling BSP.FIFO_CTRL\n"); > + nv_mask(priv, 0x103d94, 0, 0x1111); /...

This is more or less simplified series of patches that bring power usage on my NV86 close to that of binary blob. Best regards, Maxim Levitsky

...*priv, int *state) { struct nvkm_clk *clk = nvkm_clk(priv); @@ -163,32 +399,601 @@ static int gk20a_pmu_fini(struct nvkm_object *object, bool suspend) { struct nvkm_pmu *pmu = (void *)object; - struct gk20a_pmu_priv *priv = (void *)pmu; - + struct gk20a_pmu_priv *priv = to_gk20a_priv(pmu); + nv_wr32(pmu, 0x10a014, 0x00000060); + flush_work(&pmu->recv.work); nvkm_timer_alarm_cancel(priv, &priv->alarm); return nvkm_subdev_fini(&pmu->base, suspend); } static int +gk20a_pmu_enable_hw(struct nvkm_pmu *ppmu, struct nvkm_mc *pmc, + bool enable) +{ + if (enable) { + n...

...part_nr; u32 subp_nr; - struct nouveau_mm tags; u32 num_tags; + u32 tag_base; + struct nouveau_mm tags; struct nouveau_mm_node *tag_ram; }; @@ -117,10 +118,6 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv) u32 tag_size, tag_margin, tag_align; int ret; - nv_wr32(priv, 0x17e8d8, priv->part_nr); - if (nv_device(pfb)->card_type >= NV_E0) - nv_wr32(priv, 0x17e000, priv->part_nr); - /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */ priv->num_tags = (pfb->ram->size >> 17) / 4; if (priv->num_tags > (1 &lt...

...ers/gpu/drm/nouveau/core/engine/mpeg/nv31.c > index 9f7c7d5..c190043 100644 > --- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c > +++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c > @@ -284,7 +284,10 @@ nv31_mpeg_init(struct nouveau_object *object) > /* PMPEG init */ > nv_wr32(priv, 0x00b32c, 0x00000000); > nv_wr32(priv, 0x00b314, 0x00000100); > - nv_wr32(priv, 0x00b220, nv44_graph_class(priv) ? 0x00000044 : 0x00000031); > + if (nv_device(priv)->chipset >= 0x40 && nv44_graph_class(priv)) > + nv_wr32(priv, 0x00b220, 0x00000044); > + else &g...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drivers/gpu/drm/nouveau/core/engine/graph/nv40.h | 3 +++ drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c | 10 ++-------- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h index 7da35a4..ad82093 100644 ---

...n 0; >> + } >> +} >> +static void >> +gk20a_pmu_enable_irq(struct gk20a_pmu_priv *priv, struct nvkm_mc *pmc, >> bool enable) >> +{ >> + if (enable) { >> + nv_debug(priv, "enable pmu irq\n"); >> + nv_wr32(priv, 0x0010a010, 0xff); >> + nv_mask(pmc, 0x00000640, 0x1000000, 0x1000000); >> + nv_mask(pmc, 0x00000644, 0x1000000, 0x1000000); >> + } else { >> + nv_debug(priv, "disable pmu irq\n"); >> + nv_ma...

...eturn -ENOENT; + + clk_current = clk->read(clk, nv_clk_src_mem); + + ret = nva3_clock_pre(clk, f); + if (ret) + goto out; + + /* First: clock up/down */ + ret = ram->base.calc(pfb, (u32) M0205T.freq * 1000); + if (ret) + goto out; + + /* Do this *after* calc, eliminates write in script */ + nv_wr32(pfb, 0x111400, 0x00000000); + /* XXX: Magic writes that improve train reliability? */ + nv_mask(pfb, 0x100674, 0x0000ffff, 0x00000000); + nv_mask(pfb, 0x1005e4, 0x0000ffff, 0x00000000); + nv_mask(pfb, 0x100b0c, 0x000000ff, 0x00000000); + nv_wr32(pfb, 0x100c04, 0x00000400); + + /* Now the training s...

...tatic void +void nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -655,18 +655,29 @@ nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc) continue; spin_lock(&psw->peephole_lock); - nv_wr32(dev, 0x001704, pch->vblank.channel); - nv_wr32(dev, 0x001710, 0x80000000 | pch->vblank.ctxdma); - if (dev_priv->chipset == 0x50) { - nv_wr32(dev, 0x001570, pch->vblank.offset); - nv_wr32(dev, 0x001574, pch->vblank.value); + if (dev_priv->chipset < 0xc0) { + nv_wr32(dev...

...*********/ +static void +nv84_bsp_intr(struct nouveau_subdev *subdev) +{ + struct nv84_bsp_priv *priv = (void *)subdev; + u32 intr, unk104, unk10c, chan; + + unk104 = nv_rd32(priv, 0x103d04); + intr = nv_rd32(priv, 0x103c20); + chan = nv_rd32(priv, 0x103c28); + unk10c = nv_rd32(priv, 0x103d0c); + nv_wr32(priv, 0x103c20, intr); + intr = nv_rd32(priv, 0x103c20); + if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) { + nv_debug(priv, "Enabling BSP.FIFO_CTRL\n"); + nv_mask(priv, 0x103d94, 0, 0x1111); /* FIFO_CTRL */ + } +} + static int nv84_bsp_ctor(struct...

Second version of this patchset. Not many changes since first version - I hope this means the changes are not too controversial. Changes since v1: - Removed lookup for previous FW files in "nouveau/" - Went back to using request_firmware() since we only try to load one file Original cover letter follows: GM20B is the GPU of the upcoming Tegra X1 SoC. This series adds initial support

...rent, return nouveau_therm_preinit(&priv->base.base); } +static int +nv84_therm_init(struct nouveau_object *object) +{ + struct nv84_therm_priv *priv = (void *)object; + int ret; + + ret = nouveau_therm_init(&priv->base.base); + if (ret) + return ret; + + /* ACK ptherm IRQs */ + nv_wr32(object, 0x20100, 0xffffffff); + nv_wr32(object, 0x1100, 0x10000); /* PBUS */ + + return 0; +} + struct nouveau_oclass nv84_therm_oclass = { .handle = NV_SUBDEV(THERM, 0x84), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nv84_therm_ctor, .dtor = _nouveau_therm_dtor, - .init = _nouvea...