search for: nv_wr08

...etc. here so the riva_hw.* files + * HW. Put all affected includes, typdefs, etc. here so the nv_hw.* files * can stay generic in nature. */ #include "compiler.h" @@ -52,16 +52,16 @@ /* * HW access macros. These assume memory-mapped I/O, and not normal I/O space. */ -#define NV_WR08(p,i,d) MMIO_OUT8((pointer)(p), (i), (d)) -#define NV_RD08(p,i) MMIO_IN8((pointer)(p), (i)) -#define NV_WR16(p,i,d) MMIO_OUT16((pointer)(p), (i), (d)) -#define NV_RD16(p,i) MMIO_IN16((pointer)(p), (i)) -#define NV_WR32(p,i,d) MMIO_OUT32((pointer)(p), (i), (d)) -#define NV_RD32(p,i) MMIO_...

...ne void NVWriteVgaCrtc(struct drm_device *dev, int head, uint8_t index, uint8_t value) { - NV_DEBUG(dev, "NVWriteVgaCrtc: head %d index 0x%02x data 0x%02x\n", head, index, value); + NV_REG_DEBUG(VGACRTC, dev, "head %d index 0x%02x data 0x%02x\n", + head, index, value); nv_wr08(dev, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); nv_wr08(dev, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value); } @@ -192,7 +193,7 @@ NVWriteVgaCrtc(struct drm_device *dev, int head, uint8_t index, uint8_t value) static inline uint8_t NVReadVgaCrtc(struct drm_device *dev, int head,...

...eau_mc_intr(int irq, void *arg) >>>>>>>> > map++; >>>>>>>> > } >>>>>>>> > >>>>>>>> > + if (pmc->use_msi) >>>>>>>> > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); >>>>>>>> Register not present everywhere. >>>>>>>> >>>>>>>> At the very least, the enabling of MSI should be disallowed on the >>>>>>>> earlier chipsets where...

...#include <subdev/mc.h> > +#include <core/option.h> > > static irqreturn_t > nouveau_mc_intr(int irq, void *arg) > @@ -43,6 +44,9 @@ nouveau_mc_intr(int irq, void *arg) > map++; > } > > + if (pmc->use_msi) > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); Register not present everywhere. At the very least, the enabling of MSI should be disallowed on the earlier chipsets where it's not supported. Though, it's perhaps possible that the pci_enable_msi() call will fail in all of these cases anyway.....

...>>>>>>>> > map++; >>>>>>>>>> > } >>>>>>>>>> > >>>>>>>>>> > + if (pmc->use_msi) >>>>>>>>>> > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); >>>>>>>>>> Register not present everywhere. >>>>>>>>>> >>>>>>>>>> At the very least, the enabling of MSI should be disallowed on the >>>>>>>&gt...

...; map++; > >>>>>>>>>>> > } > >>>>>>>>>>> > > >>>>>>>>>>> > + if (pmc->use_msi) > >>>>>>>>>>> > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); > >>>>>>>>>>> Register not present everywhere. > >>>>>>>>>>> > >>>>>>>>>>> At the very least, the enabling of MSI should be disallowed on the >...

...void *arg) >>>>>>>>> > map++; >>>>>>>>> > } >>>>>>>>> > >>>>>>>>> > + if (pmc->use_msi) >>>>>>>>> > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); >>>>>>>>> Register not present everywhere. >>>>>>>>> >>>>>>>>> At the very least, the enabling of MSI should be disallowed on the >>>>>>>>> earlie...

...>>>> > map++; >>>>>>>>>>> > } >>>>>>>>>>> > >>>>>>>>>>> > + if (pmc->use_msi) >>>>>>>>>>> > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); >>>>>>>>>>> Register not present everywhere. >>>>>>>>>>> >>>>>>>>>>> At the very least, the enabling of MSI should be disallowed on the >>>>&gt...

...map++; >> >>>>>>>>>>> > } >> >>>>>>>>>>> > >> >>>>>>>>>>> > + if (pmc->use_msi) >> >>>>>>>>>>> > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); >> >>>>>>>>>>> Register not present everywhere. >> >>>>>>>>>>> >> >>>>>>>>>>> At the very least, the enabling of MSI should be disallowed...

...ase.c +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/base.c @@ -23,6 +23,7 @@ */ #include <subdev/mc.h> +#include <core/option.h> static irqreturn_t nouveau_mc_intr(int irq, void *arg) @@ -43,6 +44,9 @@ nouveau_mc_intr(int irq, void *arg) map++; } + if (pmc->use_msi) + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); + if (intr) { nv_error(pmc, "unknown intr 0x%08x\n", stat); } @@ -75,6 +79,8 @@ _nouveau_mc_dtor(struct nouveau_object *object) struct nouveau_device *device = nv_device(object); struct nouveau_mc *pmc = (void *)object; free_irq(de...

...lt;core/option.h> > > > > static irqreturn_t > > nouveau_mc_intr(int irq, void *arg) > > @@ -43,6 +44,9 @@ nouveau_mc_intr(int irq, void *arg) > > map++; > > } > > > > + if (pmc->use_msi) > > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); > Register not present everywhere. > > At the very least, the enabling of MSI should be disallowed on the > earlier chipsets where it's not supported. Though, it's perhaps > possible that the pci_enable_msi() call will fail in al...

...>>>>>>>>>>>>>>> } >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> + if (pmc->use_msi) >>>>>>>>>>>>>>> + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); >>>>>>>>>>>>>> Register not present everywhere. >>>>>>>>>>>>>> >>>>>>>>>>>>>> At the very least, the enabling of MSI should be d...

...>>> > @@ -43,6 +44,9 @@ nouveau_mc_intr(int irq, void *arg) >>>>>> > map++; >>>>>> > } >>>>>> > >>>>>> > + if (pmc->use_msi) >>>>>> > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); >>>>>> Register not present everywhere. >>>>>> >>>>>> At the very least, the enabling of MSI should be disallowed on the >>>>>> earlier chipsets where it's not supported. Though...

This is the first set of patches to make Nouveau work on Tegra. Those are only the obvious correctness fixes, a lot of optimization work remains to be done, but at least it's enough to get accel working and let the machine survive a piglit run. A new BO flag is introduced to allow userspace to hint the kernel about possible optimizations. Lucas Stach (6): drm/ttm: recognize ARM arch in

...gt;> > static irqreturn_t >> > nouveau_mc_intr(int irq, void *arg) >> > @@ -43,6 +44,9 @@ nouveau_mc_intr(int irq, void *arg) >> > map++; >> > } >> > >> > + if (pmc->use_msi) >> > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); >> Register not present everywhere. >> >> At the very least, the enabling of MSI should be disallowed on the >> earlier chipsets where it's not supported. Though, it's perhaps >> possible that the pci_enable_msi() c...

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...iff --git a/nvkm/subdev/mc/nv4c.c b/nvkm/subdev/mc/nv4c.c index a75c35c..165401c 100644 --- a/nvkm/subdev/mc/nv4c.c +++ b/nvkm/subdev/mc/nv4c.c @@ -24,13 +24,6 @@ #include "nv04.h" -static void -nv4c_mc_msi_rearm(struct nouveau_mc *pmc) -{ - struct nv04_mc_priv *priv = (void *)pmc; - nv_wr08(priv, 0x088050, 0xff); -} - struct nouveau_oclass * nv4c_mc_oclass = &(struct nouveau_mc_oclass) { .base.handle = NV_SUBDEV(MC, 0x4c), @@ -41,5 +34,4 @@ nv4c_mc_oclass = &(struct nouveau_mc_oclass) { .fini = _nouveau_mc_fini, }, .intr = nv04_mc_intr, - .msi_rearm = nv4c_mc_msi_re...

...rn_t >>> > nouveau_mc_intr(int irq, void *arg) >>> > @@ -43,6 +44,9 @@ nouveau_mc_intr(int irq, void *arg) >>> > map++; >>> > } >>> > >>> > + if (pmc->use_msi) >>> > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); >>> Register not present everywhere. >>> >>> At the very least, the enabling of MSI should be disallowed on the >>> earlier chipsets where it's not supported. Though, it's perhaps >>> possible that th...

It seems it was only locking up in the context of nouveau_hw_save_vga_fonts, when it actually did something (because the console wasn't already in graphics mode). Signed-off-by: Francisco Jerez <currojerez at riseup.net> --- drivers/gpu/drm/nouveau/nouveau_hw.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.c

...nouveau_mc_intr(int irq, void *arg) >>>> > @@ -43,6 +44,9 @@ nouveau_mc_intr(int irq, void *arg) >>>> > map++; >>>> > } >>>> > >>>> > + if (pmc->use_msi) >>>> > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); >>>> Register not present everywhere. >>>> >>>> At the very least, the enabling of MSI should be disallowed on the >>>> earlier chipsets where it's not supported. Though, it's perhaps >>>&...