search for: nv_rd08

Displaying 11 results from an estimated 11 matches for "nv_rd08".

2014 Mar 25
2
[PATCH 4/4] vbios/prom: fetch the vbios using only aligned 32-bit accesses
...* bail if no rom signature, with a workaround for a PROM reading * issue on some chipsets. the first read after a period of * inactivity returns the wrong result, so retry the first header @@ -164,31 +168,38 @@ nouveau_bios_shadow_prom(struct nouveau_bios *bios) */ i = 16; do { - if (nv_rd08(bios, 0x300000) == 0x55) + if ((nv_rd32(bios, 0x300000) & 0xffff) == 0xaa55) break; } while (i--); - if (!i || nv_rd08(bios, 0x300001) != 0xaa) + if (!i) goto out; - /* additional check (see note below) - read PCI record header */ - pcir = nv_rd08(bios, 0x300018) | - nv_rd0...
2014 Mar 25
0
[PATCH 4/4] vbios/prom: fetch the vbios using only aligned 32-bit accesses
...* issue on some chipsets. the first read after a period of > * inactivity returns the wrong result, so retry the first header > @@ -164,31 +168,38 @@ nouveau_bios_shadow_prom(struct nouveau_bios *bios) > */ > i = 16; > do { > - if (nv_rd08(bios, 0x300000) == 0x55) > + if ((nv_rd32(bios, 0x300000) & 0xffff) == 0xaa55) > break; > } while (i--); > > - if (!i || nv_rd08(bios, 0x300001) != 0xaa) > + if (!i) > goto out; > > - /* a...
2009 Sep 06
2
[PATCH 1/4] drm/nouveau: add reg_debug module parameter
...rtc(struct drm_device *dev, int head, uint8_t index) { nv_wr08(dev, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); - NV_DEBUG(dev, "NVReadVgaCrtc: head %d index 0x%02x data 0x%02x\n", + NV_REG_DEBUG(VGACRTC, dev, "head %d index 0x%02x data 0x%02x\n", head, index, nv_rd08(dev, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE)); return nv_rd08(dev, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE); @@ -232,7 +233,7 @@ static inline uint8_t NVReadPRMVIO(struct drm_device *dev, int head, uint32_t re if (head && nv_arch(dev) == NV_40) reg += NV_PRMVIO_SIZE; - NV_...
2007 May 24
0
[PATCH] add comments to nv_local.h
...includes, typdefs, etc. here so the nv_hw.* files * can stay generic in nature. */ #include "compiler.h" @@ -52,16 +52,16 @@ /* * HW access macros. These assume memory-mapped I/O, and not normal I/O space. */ -#define NV_WR08(p,i,d) MMIO_OUT8((pointer)(p), (i), (d)) -#define NV_RD08(p,i) MMIO_IN8((pointer)(p), (i)) -#define NV_WR16(p,i,d) MMIO_OUT16((pointer)(p), (i), (d)) -#define NV_RD16(p,i) MMIO_IN16((pointer)(p), (i)) -#define NV_WR32(p,i,d) MMIO_OUT32((pointer)(p), (i), (d)) -#define NV_RD32(p,i) MMIO_IN32((pointer)(p), (i)) +#define NV_WR08(base,offset,value)...
2009 Aug 10
1
[RFC] drm/nouveau: optimize code emission of inline functions
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2009 Jul 25
2
[RFC] patch 0/4: DRM MMIO accessor cleanup
Hi, this is continuation for the MMIO accessor rewrite and cleanup. I am currently running nv28 with these patches applied, but I cannot test on PPC. Please, review and comment. If the direction is good, I'll do the same to INSTANCE_{RD,WR} as I did for nv_{rd,wr}32, and change PRAMIN from drm_local_map to simple ioremap. Can the same be done for channel specific mappings, that is
2020 Mar 15
2
Status of GF108GLM [NVS 5200M]
Hello. I am not subscribed to the list, so, please, if I do anything wrong just let me know politely and I'll try to improve :) I just want to know if there's any branch of nouveau version that will work with this chip. lspci lists it as: 01:00.0 VGA compatible controller: NVIDIA Corporation GF108GLM [NVS 5200M] (rev a1) I think it's Fermi, but I am not sure. When I try to change
2020 Apr 10
2
Status of GF108GLM [NVS 5200M]
...n, compiler or whatever might work better for that branch is welcome though. CCLD bin/nv_rd16 CCLD bin/nv_ws32 CCLD bin/nv_ri08 CCLD bin/nv_wi32 CCLD bin/nv_wi16 CCLD bin/nv_init CCLD bin/nv_ws16 CCLD bin/nv_ri16 CCLD bin/nv_rd32 CCLD bin/nv_rd08 CCLD bin/nv_rs08 CCLD bin/nv_rv32 CCLD bin/nv_perfmon bin/nv_perfmon.c: En la funci?n ?ui_perfmon_query_signals?: bin/nv_perfmon.c:316:40: aviso: el argumento de ?sizeof? en la llamada ?strncpy? es la misma expresi?n que el origen; ?pretend?a usar el tama?o del destino? [-Wsizeof-...
2009 Aug 13
9
[PATCHv2 01/10] drm/nouveau: Fix a lock up at NVSetOwner with nv11.
It seems it was only locking up in the context of nouveau_hw_save_vga_fonts, when it actually did something (because the console wasn't already in graphics mode). Signed-off-by: Francisco Jerez <currojerez at riseup.net> --- drivers/gpu/drm/nouveau/nouveau_hw.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.c
2009 Aug 12
14
[PATCH 00/12] TV-out modesetting kernel patches.
This patch series adds TV-out modesetting support to the KMS implementation. I've tried to test it on all the hardware I've got at hand (that is nv11, nv17, nv34, nv35, nv40, nv4b) with every possible output combination; I believe it has reached a mergeable state, however it depends on some commits from drm-next that haven't got into Linus' tree yet, if you agree to merge this
2015 Jan 29
28
[Bug 88868] New: PowerPC e5500, kernel crash, GT520, GT610
...ap" is to be of the value 0x80406892, in the log it isn't reversed but there is no msd. What does the fact depend on that 2 registers are readed and one of them is reversed, but the other are not in the same time? 2. kernel crash happens by running of the code from the file base.c if (nv_rd08(bios, 0x700000) != 0x55 || nv_rd08(bios, 0x700001) != 0xaa) { It means that the address reading of 0x700000 results the kernel crash. Why does it happen? The result of the address reading of 0x619f04 is shown for the information. static void nouveau_bios_shadow_pramin(struct nouveau_bios...