search for: nv_ppwr_counter_sig_pppp_idle

...PC_IDLE 0x00000004 +#define NV_PPWR_COUNTER_SIG_GR_ROP_IDLE 0x00000008 +#define NV_PPWR_COUNTER_SIG_PVLD_IDLE 0x00000010 +#define NV_PPWR_COUNTER_SIG_PPDEC_IDLE 0x00000020 +#define NV_PPWR_COUNTER_SIG_PPPP_IDLE 0x00000040 +#define NV_PPWR_COUNTER_SIG_BFB_PART0_REQ 0x00000080 +#define NV_PPWR_COUNTER_SIG_FB_PART0_REQ 0x00000100 +#define NV_PPWR_COUNTER_SIG_PMFB 0x00001000 +#define NV_PP...

this series makes use of the load counters we can use to get information about the current load of the gpu. This series includes the needed pmu bits and a debugfs interface to read them out. Currently the values are between 0 and 255, because it is much easier to implement it this way on the pmu. Karol Herbst (4): subdev/pmu/fuc: add gk104 pmu/fuc: add macros for pdaemon pwr counters

...G_PCOPY0_IDLE + | NV_PPWR_COUNTER_SIG_PCOPY1_IDLE +#if NVKM_PPWR_CHIPSET >= GK104 + | NV_PPWR_COUNTER_SIG_PCOPY2_IDLE +#endif +#endif + ) + nv_iowr(NV_PPWR_COUNTER_MASK(1), $r14) + + // video load counter + imm32($r14, + NV_PPWR_COUNTER_SIG_PVLD_IDLE + | NV_PPWR_COUNTER_SIG_PPDEC_IDLE + | NV_PPWR_COUNTER_SIG_PPPP_IDLE +#if NVKM_PPWR_CHIPSET >= GK104 + | NV_PPWR_COUNTER_SIG_PVENC +#endif + ) + nv_iowr(NV_PPWR_COUNTER_MASK(2), $r14) + + // memory load counter + imm32($r14, +#if NVKM_PPWR_CHIPSET >= GF100 + NV_PPWR_COUNTER_SIG_BFB_PART0_REQ +#else + NV_PPWR_COUNTER_SIG_FB_PART0_REQ +#endif + ) + nv_iow...