search for: nv_ppwr_counter_sig_pcopy2_idle

...0x00001000 +#define NV_PPWR_COUNTER_SIG_PVENC 0x00020000 +#define NV_PPWR_COUNTER_SIG_PCOPY0_IDLE 0x00080000 +#define NV_PPWR_COUNTER_SIG_PCOPY1_IDLE 0x00100000 +#define NV_PPWR_COUNTER_SIG_PCOPY2_IDLE 0x00200000 +#define NV_PPWR_COUNTER_SIG_PCIE 0x20000000 #if NVKM_PPWR_CHIPSET < GK208 #define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x05d0) #endif -- 2.6.2

this series makes use of the load counters we can use to get information about the current load of the gpu. This series includes the needed pmu bits and a debugfs interface to read them out. Currently the values are between 0 and 255, because it is much easier to implement it this way on the pmu. Karol Herbst (4): subdev/pmu/fuc: add gk104 pmu/fuc: add macros for pdaemon pwr counters

...($r14, + NV_PPWR_COUNTER_SIG_GR_IDLE + | NV_PPWR_COUNTER_SIG_GR_GPC_IDLE + | NV_PPWR_COUNTER_SIG_GR_ROP_IDLE +#if NVKM_PPWR_CHIPSET >= GF100 + | NV_PPWR_COUNTER_SIG_GR_HUB_IDLE + | NV_PPWR_COUNTER_SIG_PCOPY0_IDLE + | NV_PPWR_COUNTER_SIG_PCOPY1_IDLE +#if NVKM_PPWR_CHIPSET >= GK104 + | NV_PPWR_COUNTER_SIG_PCOPY2_IDLE +#endif +#endif + ) + nv_iowr(NV_PPWR_COUNTER_MASK(1), $r14) + + // video load counter + imm32($r14, + NV_PPWR_COUNTER_SIG_PVLD_IDLE + | NV_PPWR_COUNTER_SIG_PPDEC_IDLE + | NV_PPWR_COUNTER_SIG_PPPP_IDLE +#if NVKM_PPWR_CHIPSET >= GK104 + | NV_PPWR_COUNTER_SIG_PVENC +#endif + ) + nv_iowr(NV_P...