search for: nv_ppwr_counter_count_reset

...0x04d0 #define NV_PPWR_D2H 0x04dc +#define NV_PPWR_COUNTER_MASK(i) (0x10 * (i) + 0x0504) +#define NV_PPWR_COUNTER_COUNT(i) (0x10 * (i) + 0x0508) +#define NV_PPWR_COUNTER_COUNT_RESET 0x80000000 +#define NV_PPWR_COUNTER_MODE(i) (0x10 * (i) + 0x050c) +#define NV_PPWR_COUNTER_MODE_NEVER 0 +#define NV_PPWR_COUNTER_MODE_IF_ALL 1 +#define NV...

...0x04d0 #define NV_PPWR_D2H 0x04dc +#define NV_PPWR_COUNTER_MASK(i) (0x10 * (i) + 0x0504) +#define NV_PPWR_COUNTER_COUNT(i) (0x10 * (i) + 0x0508) +#define NV_PPWR_COUNTER_COUNT_RESET 0x80000000 +#define NV_PPWR_COUNTER_MODE(i) (0x10 * (i) + 0x050c) +#define NV_PPWR_COUNTER_MODE_NEVER 0 +#define NV_PPWR_COUNTER_MODE_IF_ALL 1 +#define NV...

this series makes use of the load counters we can use to get information about the current load of the gpu. This series includes the needed pmu bits and a debugfs interface to read them out. Currently the values are between 0 and 255, because it is much easier to implement it this way on the pmu. Karol Herbst (4): subdev/pmu/fuc: add gk104 pmu/fuc: add macros for pdaemon pwr counters

these are usually used for dynamic reclocking on gt215 and newer The counters are used to get the load of the core, memory, video and pcie loads currently I expose the loads through a debugfs "current_load" file, but I want to move that to nvif and just add a wrapper around that in debugfs for convenience Anyway there are still some issues I would like to discuss: 1. currently the

these are usually used for dynamic reclocking on gt215 and newer The counters are used to get the load of the core, memory, video and pcie loads currently I expose the loads through a debugfs "current_load" file, but I want to move that to nvif and just add a wrapper around that in debugfs for convenience. Using nvif would have the advantage, that userspace tools can easily get loads

...(b8, #perf_eng_vdec, $r13) + + nv_iord($r13, NV_PPWR_COUNTER_COUNT(3)) + div $r13 $r13 $r14 + st(b8, #perf_eng_mc, $r13) + +#if NVKM_PPWR_CHIPSET >= GF100 + nv_iord($r13, NV_PPWR_COUNTER_COUNT(4)) + div $r13 $r13 $r14 + st(b8, #perf_eng_pcie, $r13) +#endif + + // reset the counters + imm32($r14, NV_PPWR_COUNTER_COUNT_RESET) + nv_iowr(NV_PPWR_COUNTER_COUNT(0), $r14) + nv_iowr(NV_PPWR_COUNTER_COUNT(1), $r14) + nv_iowr(NV_PPWR_COUNTER_COUNT(2), $r14) + nv_iowr(NV_PPWR_COUNTER_COUNT(3), $r14) +#if NVKM_PPWR_CHIPSET >= GF100 + nv_iowr(NV_PPWR_COUNTER_COUNT(4), $r14) +#endif + ret // description @@ -53,5 +137,69 @@...

reworked this series quite a lot. Now we want the Host to configure the counters through the PMU. The series isn't complete though because it needs: 1. reordering 2. better commit messages but I felt like sending those out before doing a final version. I also found some weird register overwriting issue on the PMU I have to track down, because it interfers with the counter read out. I am

I think I am done reworking the series and getting to a point where I think it is basically finished. The configuration of the slots could be improved later on when working on dynamic reclocking, but for now it's good enough to report the current GPU utilization to userspace. Patches 1-4 imeplement PMU commands to setup and readout the counters. Patches 5-6 lets Nouveau make use of 1-4. Patch