Displaying 3 results from an estimated 3 matches for "nv_pfifo_intr_cache_error".
2012 Dec 09
0
[PATCH 1/4] drm/nouveau: split fifo interrupt handler
...));
+ }
+
+ if (!nv04_fifo_swmthd(priv, chid, mthd, data)) {
+ nv_error(priv,
+ "CACHE_ERROR - Ch %d/%d Mthd 0x%04x Data 0x%08x\n",
+ chid, (mthd >> 13) & 7, mthd & 0x1ffc, data);
+ }
+
+ nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
+ nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
+
+ nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0,
+ nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) & ~1);
+ nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4);
+ nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0,
+ nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) | 1);
+ nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0);
+
+ nv_wr32(priv, N...
2010 Mar 11
5
Interrupt setting
...are ways
to set GPU to send interrupts to CPU, when we want to be notified for
something, e.g., when DMA transfer or GPU operation is completed.
By default, when I run an OpenGL demo application from Gallium3D, the driver
gets no interrupts from GPU in nouveau_irq_handler(), except that it gets
one NV_PFIFO_INTR_CACHE_ERROR interrupt right after the FIFO is allocated.
According to the wiki docs, I need to set
NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN into the 'notify'
field of an object in a channel.
Hence, I tried seting a flag to a DMA notifier in nouveau_dma_init():
// seems entry[1] is relat...
2007 Jun 22
0
[PATCH] Commented out all macros that are not used - it still compiles.
...-#define NV04_PFIFO_NEXT_CHANNEL 0x00002050
+// #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
#define NV03_PFIFO_INTR_0 0x00002100
#define NV03_PFIFO_INTR_EN_0 0x00002140
# define NV_PFIFO_INTR_CACHE_ERROR (1<< 0)
@@ -325,77 +325,77 @@
#define NV03_PFIFO_CACHE1_PUSH1 0x00003204
#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220
#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224
-# define NV_PFIFO_CACH...