Displaying 3 results from an estimated 3 matches for "nv_pdisp_clk_rem_link_ctrl".
2014 Dec 09
2
DCB 4.1 spec update
On Wed, Dec 10, 2014 at 7:36 AM, Ben Skeggs <skeggsb at gmail.com> wrote:
> On Wed, Dec 10, 2014 at 4:26 AM, Andy Ritger <aritger at nvidia.com> wrote:
>> Hi,
> Hey Andy,
>
>>
>> The VBIOS on GM20x GPUs uses a slightly updated version of the DCB.
>> I've posted an updated DCB spec here:
>>
>>
2014 Dec 14
1
DCB 4.1 spec update
...t; Macro Link. The Macro Links are labeled A - G.
>
> In GM20x, we added an "SOR Crossbar" between the SORs and the Macros,
> such that any SOR Sublink can drive any Macro Link.
>
> The registers to control the SOR Crossbar are 0x00612308+(i)*128:
>
> #define NV_PDISP_CLK_REM_LINK_CTRL(i) (0x00612308+(i)*128) /* RW-4A */
> #define NV_PDISP_CLK_REM_LINK_CTRL__SIZE_1 7 /* */
> #define NV_PDISP_CLK_REM_LINK_CTRL_FRONTEND 3:0 /* RWIVF */
> #def...
2014 Dec 13
0
DCB 4.1 spec update
...inks each, and the fourth has one
Macro Link. The Macro Links are labeled A - G.
In GM20x, we added an "SOR Crossbar" between the SORs and the Macros,
such that any SOR Sublink can drive any Macro Link.
The registers to control the SOR Crossbar are 0x00612308+(i)*128:
#define NV_PDISP_CLK_REM_LINK_CTRL(i) (0x00612308+(i)*128) /* RW-4A */
#define NV_PDISP_CLK_REM_LINK_CTRL__SIZE_1 7 /* */
#define NV_PDISP_CLK_REM_LINK_CTRL_FRONTEND 3:0 /* RWIVF */
#define NV_PDISP_CL...