search for: nv_oclass

Displaying 8 results from an estimated 8 matches for "nv_oclass".

2014 Dec 23
2
[PATCH V2 2/4] pwr: make nouveau_pwr_pgob() non-static
...00644 > --- a/nvkm/subdev/pwr/base.c > +++ b/nvkm/subdev/pwr/base.c > @@ -26,7 +26,7 @@ > > #include "priv.h" > > -static void > +void > nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable) > { > const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr); > diff --git a/nvkm/subdev/pwr/priv.h b/nvkm/subdev/pwr/priv.h > index 3814a341db32..86149d9a440c 100644 > --- a/nvkm/subdev/pwr/priv.h > +++ b/nvkm/subdev/pwr/priv.h > @@ -26,6 +26,7 @@ int _nouveau_pwr_ctor(struct nouveau_object *, struct nouveau_object *, > #define _no...
2015 Mar 11
0
[PATCH] pmu/gk20a: PMU boot support.
...return true; > + } > + } > + *hex_pos = -1; > + return false; > +} > +static int falc_trace_show(struct seq_file *s, void *data) > +{ > + struct nvkm_pmu *ppmu = s->private; > + struct nvkm_pmu_impl *impl = (void *)nv_oclass(ppmu); > + struct pmu_desc *pmu = &impl->pmudata; > + u32 i = 0, j = 0, k, l, m; > + char part_str[40]; > + u32 data1; > + char *log_data = kmalloc(GK20A_PMU_TRACE_BUFSIZE, GFP_KERNEL); > + char *trace = log_data; > + u32 *trace1...
2015 Mar 11
3
[PATCH] pmu/gk20a: PMU boot support.
...+ if (strings[i + 1] == 'x' || strings[i + 1] == 'X') { + *hex_pos = i; + return true; + } + } + *hex_pos = -1; + return false; +} +static int falc_trace_show(struct seq_file *s, void *data) +{ + struct nvkm_pmu *ppmu = s->private; + struct nvkm_pmu_impl *impl = (void *)nv_oclass(ppmu); + struct pmu_desc *pmu = &impl->pmudata; + u32 i = 0, j = 0, k, l, m; + char part_str[40]; + u32 data1; + char *log_data = kmalloc(GK20A_PMU_TRACE_BUFSIZE, GFP_KERNEL); + char *trace = log_data; + u32 *trace1 = (u32 *)log_data; + for (i = 0; i < GK20A_PMU_TRACE_BUFSIZE; i += 4) { +...
2015 Mar 12
2
[PATCH] pmu/gk20a: PMU boot support.
...return true; > + } > + } > + *hex_pos = -1; > + return false; > +} > +static int falc_trace_show(struct seq_file *s, void *data) > +{ > + struct nvkm_pmu *ppmu = s->private; > + struct nvkm_pmu_impl *impl = (void *)nv_oclass(ppmu); > + struct pmu_desc *pmu = &impl->pmudata; > + u32 i = 0, j = 0, k, l, m; > + char part_str[40]; > + u32 data1; > + char *log_data = kmalloc(GK20A_PMU_TRACE_BUFSIZE, GFP_KERNEL); > + char *trace = log_data; > + u32 *trace1...
2014 Dec 22
0
[PATCH V2 2/4] pwr: make nouveau_pwr_pgob() non-static
...c b/nvkm/subdev/pwr/base.c index 0ab55f27ec45..1ea433a5e118 100644 --- a/nvkm/subdev/pwr/base.c +++ b/nvkm/subdev/pwr/base.c @@ -26,7 +26,7 @@ #include "priv.h" -static void +void nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable) { const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr); diff --git a/nvkm/subdev/pwr/priv.h b/nvkm/subdev/pwr/priv.h index 3814a341db32..86149d9a440c 100644 --- a/nvkm/subdev/pwr/priv.h +++ b/nvkm/subdev/pwr/priv.h @@ -26,6 +26,7 @@ int _nouveau_pwr_ctor(struct nouveau_object *, struct nouveau_object *, #define _nouveau_pwr_dtor _nouveau_subdev_...
2015 Jan 04
0
[PATCH V2 2/4] pwr: make nouveau_pwr_pgob() non-static
...dev/pwr/base.c >> +++ b/nvkm/subdev/pwr/base.c >> @@ -26,7 +26,7 @@ >> #include "priv.h" >> -static void >> +void >> nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable) >> { >> const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr); >> diff --git a/nvkm/subdev/pwr/priv.h b/nvkm/subdev/pwr/priv.h >> index 3814a341db32..86149d9a440c 100644 >> --- a/nvkm/subdev/pwr/priv.h >> +++ b/nvkm/subdev/pwr/priv.h >> @@ -26,6 +26,7 @@ int _nouveau_pwr_ctor(struct nouveau_object *, struct >> nouveau...
2014 Dec 22
7
[PATCH V2 1/4] clk: allow non-blocking for nouveau_clock_astate()
There might be some callers of nouveau_clock_astate(), and they are from inetrrupt context. So we must ensure that this function can be atomic in that condition. This patch adds one parameter which is subsequently passed to nouveau_pstate_calc(). Therefore we can choose whether we want to wait for the pstate work's completion or not. Signed-off-by: Vince Hsu <vinceh at nvidia.com> ---
2013 Feb 03
1
3.8-rc6: nouveau lockdep recursive lock acquisition
>From recent additional locking in nouveau, it looks like we see recursive lock acquisition in 3.8-rc6: nouveau [ DEVICE][0000:01:00.0] BOOT0 : 0x0e7150a2 nouveau [ DEVICE][0000:01:00.0] Chipset: GK107 (NVE7) nouveau [ DEVICE][0000:01:00.0] Family : NVE0 nouveau [ VBIOS][0000:01:00.0] checking PRAMIN for image... nouveau [ VBIOS][0000:01:00.0] ... appears to be valid nouveau [