Displaying 7 results from an estimated 7 matches for "nv_mem_access_nosnoop".
2013 Aug 28
1
[PATCH 4/6] drm/nouveau: introduce NOUVEAU_GEM_TILE_WCUS
...if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
> nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
> else if (nvbo->bo.mem.mem_type == TTM_PL_TT) {
> + if (!(nvbo->valid_caching & TTM_PL_FLAG_CACHED))
> + vma->access |= NV_MEM_ACCESS_NOSNOOP;
> +
> if (node->sg)
> nouveau_vm_map_sg_table(vma, 0, size, node);
> else
> diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h
> index 653dbbb..2ecf8b7 100644
> --- a/drivers/gpu/d...
2013 Aug 28
0
[PATCH 4/6] drm/nouveau: introduce NOUVEAU_GEM_TILE_WCUS
...@@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
else if (nvbo->bo.mem.mem_type == TTM_PL_TT) {
+ if (!(nvbo->valid_caching & TTM_PL_FLAG_CACHED))
+ vma->access |= NV_MEM_ACCESS_NOSNOOP;
+
if (node->sg)
nouveau_vm_map_sg_table(vma, 0, size, node);
else
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h
index 653dbbb..2ecf8b7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.h
@@ -9,6 +9,7 @...
2013 Aug 28
11
[PATCH 0/6] Nouveau on ARM fixes
This is the first set of patches to make Nouveau work
on Tegra. Those are only the obvious correctness fixes,
a lot of optimization work remains to be done, but at least
it's enough to get accel working and let the machine survive
a piglit run.
A new BO flag is introduced to allow userspace to hint the
kernel about possible optimizations.
Lucas Stach (6):
drm/ttm: recognize ARM arch in
2014 Apr 17
0
[PATCH] drm/nouveau: add some basic debugfs dumping for nouveau's clients and vm mappings
...ess(char *ba, u32 access)
+{
+ if (access & NV_MEM_ACCESS_RO)
+ *ba++ = 'R';
+ else
+ *ba++ = '-';
+
+ if (access & NV_MEM_ACCESS_WO)
+ *ba++ = 'W';
+ else
+ *ba++ = '-';
+
+ if (access & NV_MEM_ACCESS_SYS)
+ *ba++ = 'S';
+
+ if (access & NV_MEM_ACCESS_NOSNOOP)
+ *ba++ = 'N';
+
+ *ba = 0;
+}
+
+static const char *nouveau_get_mapping(enum nouveau_vma_mapping mapping)
+{
+ switch (mapping) {
+ case NOUVEAU_MAP_UNMAPPED: return "unmapped";
+ case NOUVEAU_MAP_SG: return "sgt ";
+ case NOUVEAU_MAP_GART: return "gart";
+...
2015 Apr 16
2
[PATCH 6/6] mmu: gk20a: implement IOMMU mapping for big pages
...; + u64 iova;
> +};
> +
> +extern const u8 gf100_pte_storage_type_map[256];
> +
> +static void
> +gk20a_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
> + struct nvkm_mem *mem, u32 pte, u64 list)
> +{
> + u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5;
> + u64 phys;
> +
> + pte <<= 3;
> + phys = gf100_vm_addr(vma, list, mem->memtype, target);
> +
> + if (mem->tag) {
> + struct nvkm_ltc *ltc = nvkm_ltc(vma->vm->mmu);
> + u32 tag = mem->tag-&g...
2013 Mar 27
3
[PATCH 1/4] drm/nvc0: implement VRAM compression
...t--) {
nv_wo32(pgt, pte + 0, lower_32_bits(phys));
nv_wo32(pgt, pte + 4, upper_32_bits(phys));
@@ -85,10 +137,12 @@ nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5;
+ /* compressed storage types are invalid for system memory */
+ u32 memtype = nvc0_pte_storage_type_map[mem->memtype & 0xff];
pte <<= 3;
while (cnt--) {
- u64 phys = nvc0_vm_addr(vma, *list++, mem->memtype, target);
+ u64 phys = nvc0_vm_addr(vma, *list++, memtype,...
2015 Apr 16
15
[PATCH 0/6] map big page by platform IOMMU
Hi,
Generally the the imported buffers which has memory type TTM_PL_TT are
mapped as small pages probably due to lack of big page allocation. But the
platform device which also use memory type TTM_PL_TT, like GK20A, can
*allocate* big page though the IOMMU hardware inside the SoC. This is a try
to map the imported buffers as big pages in GMMU by the platform IOMMU. With
some preparation work to