search for: nv_gpuobj

...ore/core/ramht.c b/drivers/gpu/drm/nouveau/core/core/ramht.c index 86a6404..6da314c 100644 --- a/drivers/gpu/drm/nouveau/core/core/ramht.c +++ b/drivers/gpu/drm/nouveau/core/core/ramht.c @@ -59,7 +59,7 @@ nouveau_ramht_insert(struct nouveau_ramht *ramht, int chid, } co += 8; - if (co >= nv_gpuobj(ramht)->size) + if (co + 8 > nv_gpuobj(ramht)->size) co = 0; } while (co != ho); -- 1.8.0.2

Signed-off-by: Marcin Slusarz <marcin.slusarz at gmail.com> --- drivers/gpu/drm/nouveau/core/core/gpuobj.c | 6 +++++- drivers/gpu/drm/nouveau/core/include/core/gpuobj.h | 3 +++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/core/core/gpuobj.c b/drivers/gpu/drm/nouveau/core/core/gpuobj.c index c2a7608..48121d2 100644 ---

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Not 100% sure that this is needed, but BSP/MPEG are in the mask. drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c index 0cb322a..f25fc5f 100644 ---

...ruct nouveau_disp *disp = nouveau_disp(engine); + int ret, i; ret = nouveau_software_context_create(parent, engine, oclass, &chan); *pobject = nv_object(chan); @@ -169,16 +170,36 @@ nv50_software_context_ctor(struct nouveau_object *parent, return ret; chan->base.vblank.channel = nv_gpuobj(parent->parent)->addr >> 12; - chan->base.vblank.event.func = nv50_software_vblsem_release; + for (i = 0; i < ARRAY_SIZE(chan->base.vblank.event); i++) { + nouveau_event_handler_install(disp->vblank, i, + nv50_software_vblsem_release, + NULL, +...

...); + if (ret) + goto fw_alloc_err; + + ucode_image = (u32 *)((u8 *)desc + desc->descriptor_size); + for (i = 0; i < (desc->app_start_offset + desc->app_size); i += 4) + nv_wo32(pmu->ucode.obj, i, ucode_image[i/4]); + + /* map allocated memory into GMMU */ + ret = nvkm_gpuobj_map_vm(nv_gpuobj(pmu->ucode.obj), vm, + NV_MEM_ACCESS_RW, &pmu->ucode.vma); + if (ret) + goto map_err; + + nv_debug(ppmu, "%s function end\n", __func__); + return ret; +map_err: + nvkm_gpuobj_destroy(pmu->ucode.obj); +fw_alloc_err: + nvkm_gpuobj_destroy(ppmuvm->pgd); +pgd_alloc_err...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c index c190043..5c54aa1 100644 --- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c +++

...priv_vm *pmuvm = &priv->pmuvm; + int ret = 0; + + INIT_WORK(&priv->base.recv.work, gk20a_pmu_process_message); + + ret = nvkm_gpuobj_new(nv_object(priv), NULL, GK20A_PMU_TRACE_BUFSIZE, + 0, 0, &priv->trace_buf.obj); + if (ret) + return ret; + + ret = nvkm_gpuobj_map_vm(nv_gpuobj(priv->trace_buf.obj), pmuvm->vm, + NV_MEM_ACCESS_RW, &priv->trace_buf.vma); + if (ret) + return ret; + + return 0; +} + +static int +gk20a_pmu_bootstrap(struct gk20a_pmu_priv *priv) +{ + struct pmu_ucode_desc *desc = priv->desc; + u32 addr_code, addr_data, addr_load; + u32 i, b...

...sc->app_size) >> 2; i++) { > + nv_wo32(pmu->ucode.pmubufobj, i << 2, ucode_image[i]); > + pr_info("writing 0x%08x\n", ucode_image[i]); > + } > + /* map allocated memory into GMMU */ > + ret = nvkm_gpuobj_map_vm(nv_gpuobj(pmu->ucode.pmubufobj), vm, > + NV_MEM_ACCESS_RW, > + &pmu->ucode.pmubufvma); > + if (ret) > + goto map_err; > + > + nv_debug(ppmu, "%s function end\n", __func__); >...

...escriptor_size); + for (i = 0; i < (desc->app_start_offset + desc->app_size) >> 2; i++) { + nv_wo32(pmu->ucode.pmubufobj, i << 2, ucode_image[i]); + pr_info("writing 0x%08x\n", ucode_image[i]); + } + /* map allocated memory into GMMU */ + ret = nvkm_gpuobj_map_vm(nv_gpuobj(pmu->ucode.pmubufobj), vm, + NV_MEM_ACCESS_RW, + &pmu->ucode.pmubufvma); + if (ret) + goto map_err; + + nv_debug(ppmu, "%s function end\n", __func__); + return ret; +map_err: + nvkm_gpuobj_destroy(pmu->ucode.pmubufobj); +virt_alloc_err: +fw_alloc_err: + nvkm_gp...

...sc->app_size) >> 2; i++) { > + nv_wo32(pmu->ucode.pmubufobj, i << 2, ucode_image[i]); > + pr_info("writing 0x%08x\n", ucode_image[i]); > + } > + /* map allocated memory into GMMU */ > + ret = nvkm_gpuobj_map_vm(nv_gpuobj(pmu->ucode.pmubufobj), vm, > + NV_MEM_ACCESS_RW, > + &pmu->ucode.pmubufvma); > + if (ret) > + goto map_err; > + > + nv_debug(ppmu, "%s function end\n", __func__); >...

This series was originally motivated by a deadlock, introduced in commit 1d7c71a3e2f77336df536855b0efd2dc5bdeb41b 'drm/nouveau/disp: port vblank handling to event interface', due to inverted lock order between nouveau_drm_vblank_enable() and nouveau_drm_vblank_handler() (the complete lockdep report is included in the patch 4/5 changelog). Because this series fixes the vblank event

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drivers/gpu/drm/nouveau/nouveau_connector.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h index 6e399aa..4cefce3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.h +++ b/drivers/gpu/drm/nouveau/nouveau_connector.h @@ -107,7 +107,4

Hi there, Resending these now that they've had some more polish and testing, and I heard that Ben's vacation is over :-) These patches work as a starting point for more explicit error mechanisms and better robustness. At the moment, when a job hangs or faults, it seems that nouveau doesn't quite know how to handle the situation and often results in a hang. Some of these situations

...gt;> + ret = nvkm_gpuobj_new(nv_object(priv), NULL, >> GK20A_PMU_TRACE_BUFSIZE, >> + 0, 0, &priv->trace_buf.obj); >> + if (ret) >> + return ret; >> + >> + ret = nvkm_gpuobj_map_vm(nv_gpuobj(priv->trace_buf.obj), >> pmuvm->vm, >> + NV_MEM_ACCESS_RW, >> &priv->trace_buf.vma); >> + if (ret) >> + return ret; >> + >> + return 0; >> +} >> + >> +static int...

Hello, This series exposes global performance counters (PCOUNTER) to the userspace through the nvif interface by reworking most of the code related to the PM engine. This interface will allow the userspace to control and monitor complex hardware events like the proprietary driver already does, for example with CUPTI and PerfKit. For now, this series only exposes performance counters on NV50,