search for: nv_engin

...= nouveau_xtensa_create(parent, engine, oclass, 0x103000, true, "PBSP", "bsp", &priv); *pobject = nv_object(priv); if (ret) @@ -78,6 +74,10 @@ nv84_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_subdev(priv)->unit = 0x04008000; nv_engine(priv)->cclass = &nv84_bsp_cclass; nv_engine(priv)->sclass = nv84_bsp_sclass; + priv->fifo_val = 0x1111; + priv->fifo_nibble = 7; + priv->unkd28 = 0x90044; + priv->firmware_fname = "nouveau/nv84_bsp"; return 0; } @@ -86,8 +86,10 @@ nv84_bsp_oclass = { .handl...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c index c190043..5c54aa1 100644 --- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c +++

...pos = vline; + *hpos = hline; + return 0; +} + static int nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, @@ -1302,6 +1353,9 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_engine(priv)->sclass = nv50_disp_base_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nv50_disp_intr; + priv->base.max_vblank_count = 0xffff; + priv->base.get_vblank_count = nv50_disp_get_vblank_count; + priv->base.get_scanoutpos = nv50_disp_get_scan...

...veau_device *device = nv_device(parent); ret = nouveau_engine_create(parent, engine, oclass, true, "PBSP", "bsp", &priv); @@ -78,16 +120,105 @@ nv84_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_subdev(priv)->unit = 0x04008000; nv_engine(priv)->cclass = &nv84_bsp_cclass; nv_engine(priv)->sclass = nv84_bsp_sclass; + + ret = request_firmware(&fw, "nouveau/nv84_bsp", &device->pdev->dev); + if (ret) { + nv_warn(priv, "Firmware for NV84 BSP unavailable.\n"); + return 0; + } + + nv_subdev(...

Hi folks, This set of patches is just for clearing the way before introducing the infrastructure for performance counters in perfmon. I'll try to publish a new version of my kernel interface based on nvif in a couple of days. See you.

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drivers/gpu/drm/nouveau/nouveau_connector.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h index 6e399aa..4cefce3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.h +++ b/drivers/gpu/drm/nouveau/nouveau_connector.h @@ -107,7 +107,4

...engine_create(parent, engine, oclass, true, > "PBSP", "bsp", &priv); > @@ -78,16 +120,105 @@ nv84_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, > nv_subdev(priv)->unit = 0x04008000; > nv_engine(priv)->cclass = &nv84_bsp_cclass; > nv_engine(priv)->sclass = nv84_bsp_sclass; > + > + ret = request_firmware(&fw, "nouveau/nv84_bsp", &device->pdev->dev); > + if (ret) { > + nv_warn(priv, "Firmware for NV84 BS...

--- drivers/gpu/drm/nouveau/core/include/subdev/ltcg.h | 7 + drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c | 55 +++++---- drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c | 129 +++++++++++++++++++- drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c | 58 +++++++++- 4 files changed, 220 insertions(+), 29 deletions(-) diff --git

...index b751d0dc4bf3..34b6d4baea16 100644 --- a/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drm/nouveau/nvkm/engine/gr/gf100.c @@ -241,7 +241,7 @@ static int gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd, void *pdata, u32 size) { - struct gf100_gr_priv *priv = (void *)nv_engine(object); + struct gf100_gr_priv *priv = (void *)object->engine; if (size >= sizeof(u32)) { u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000; nv_wr32(priv, 0x419e44, data); -- 2.3.0

...*priv; int ret; - ret = nouveau_engine_create(parent, engine, oclass, true, + ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true, "PBSP", "bsp", &priv); *pobject = nv_object(priv); if (ret) @@ -86,8 +102,10 @@ nv98_bsp_oclass = { .handle = NV_ENGINE(BSP, 0x98), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nv98_bsp_ctor, - .dtor = _nouveau_engine_dtor, - .init = _nouveau_engine_init, - .fini = _nouveau_engine_fini, + .dtor = _nouveau_falcon_dtor, + .init = nv98_bsp_init, + .fini = _nouveau_falcon_fini, + .rd32 = _nouveau_falcon...

Reclocking of NVAA/NVAC is substantially different from NV50+, enough to justify a separate clock implementation. This code is a forward-port of reclocking code that has been sitting in a branch for a while, and has been tested on my NVAC. Traces show no significant reasons why this shouldn't work on NVAA, but testers are always welcome. And since these are IGPs without dedicated RAM to

...s && sclass->ofuncs) { + if (sclass && sclass->ofuncs) { nclass = kzalloc(sizeof(*nclass), GFP_KERNEL); if (!nclass) return -ENOMEM; @@ -94,7 +94,6 @@ nouveau_parent_create_(struct nouveau_object *parent, object->sclass = nclass; nclass->engine = engine ? nv_engine(engine) : NULL; nclass->oclass = sclass; - sclass++; } object->engine = engcls; diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/device.h b/drivers/gpu/drm/nouveau/core/include/subdev/device.h index c9e4c4a..0966f33 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/d...

...+ b/drivers/gpu/drm/nouveau/core/core/parent.c @@ -49,7 +49,7 @@ nouveau_parent_sclass(struct nouveau_object *parent, u16 handle, mask = nv_parent(parent)->engine; while (mask) { - int i = ffsll(mask) - 1; + int i = __ffs64(mask); if (nv_iclass(parent, NV_CLIENT_CLASS)) engine = nv_engine(nv_client(parent)->device); diff --git a/drivers/gpu/drm/nouveau/core/os.h b/drivers/gpu/drm/nouveau/core/os.h index 191e739..3cd6120 100644 --- a/drivers/gpu/drm/nouveau/core/os.h +++ b/drivers/gpu/drm/nouveau/core/os.h @@ -23,17 +23,6 @@ #include <asm/unaligned.h> -static inline in...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Not 100% sure that this is needed, but BSP/MPEG are in the mask. drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c index 0cb322a..f25fc5f 100644 ---

Second version of this patchset. Not many changes since first version - I hope this means the changes are not too controversial. Changes since v1: - Removed lookup for previous FW files in "nouveau/" - Went back to using request_firmware() since we only try to load one file Original cover letter follows: GM20B is the GPU of the upcoming Tegra X1 SoC. This series adds initial support

Hello everyone, GM20B is the GPU of the upcoming Tegra X1 SoC. This series adds initial support for it, based on a rework of the already-supported GK20A. It also introduces support for NVIDIA-provided firmware files, which is why I have added a few NVIDIA people who are relevant to this discussion. The first patch adds support for loading the FECS and GPCCS firmwares from firmware files

...u_vma dispc_vma[4]; + u32 class[8]; }; u64 @@ -67,6 +68,40 @@ nvc0_software_method(struct drm_device *dev, u32 chid, u32 class, u32 mthd, u32 return handled; } +bool +nve0_software_method(struct drm_device *dev, u32 chid, u32 subc, u32 mthd, u32 data) +{ + struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO); + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nvc0_software_chan *pch; + struct nouveau_channel *chan; + unsigned long flags; + bool handled = false; + + spin_lock_irqsave(&dev_priv->channels.lock, flags); + if (chid >= pfifo->channels...

...ruct nouveau_oclass nv31_mpeg_sclass[] = { - { 0x3174, &nv31_mpeg_ofuncs, nv31_mpeg_omthds }, + { 0x3174, &nv31_mpeg_ofuncs }, {} }; @@ -208,7 +202,6 @@ nv31_mpeg_intr(struct nouveau_subdev *subdev) struct nouveau_fifo *pfifo = nouveau_fifo(subdev); struct nouveau_engine *engine = nv_engine(subdev); struct nouveau_object *engctx; - struct nouveau_handle *handle; struct nv31_mpeg_priv *priv = (void *)subdev; u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff; u32 stat = nv_rd32(priv, 0x00b100); @@ -229,10 +222,8 @@ nv31_mpeg_intr(struct nouveau_subdev *subdev) } if (t...

...length, pobject); + device = *pobject; + if (ret) + goto done; + + device->platformdev = pdev; + device->handle = name; + device->cfgopt = cfg; + device->dbgopt = dbg; + device->name = sname; + + nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE"); + nv_engine(device)->sclass = nouveau_device_sclass; + list_add(&device->head, &nv_devices); +done: + mutex_unlock(&nv_devices_mutex); + return ret; +} diff --git a/drivers/gpu/drm/nouveau/core/include/engine/device.h b/drivers/gpu/drm/nouveau/core/include/engine/device.h index b3dd2c4..9005...

...NY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include "nve0.h" + +struct nouveau_oclass * +nvea_fifo_oclass = &(struct nve0_fifo_impl) { + .base.handle = NV_ENGINE(FIFO, 0xea), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nve0_fifo_ctor, + .dtor = nve0_fifo_dtor, + .init = nve0_fifo_init, + .fini = nve0_fifo_fini, + }, + .channels = 128, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/i...