search for: nv_e0

...struct nouveau_mm tags; struct nouveau_mm_node *tag_ram; }; @@ -117,10 +118,6 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv) u32 tag_size, tag_margin, tag_align; int ret; - nv_wr32(priv, 0x17e8d8, priv->part_nr); - if (nv_device(pfb)->card_type >= NV_E0) - nv_wr32(priv, 0x17e000, priv->part_nr); - /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */ priv->num_tags = (pfb->ram->size >> 17) / 4; if (priv->num_tags > (1 << 17)) @@ -152,7 +149,7 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, stru...

.../drivers/gpu/drm/nouveau/nouveau_drm.c [...] > + if (device->chipset == 0xea) { > + /* gk20a does not have CE0/CE1 */ This would be another good candidate for a feature flag. > + arg0 = NVE0_CHANNEL_IND_ENGINE_GR; > + arg1 = 1; > + } else > if (device->card_type >= NV_E0) { The formatting here is somewhat weird. From a brief look I couldn't find any indication that nouveau deviates from the standard coding style, so this should be: } else if (...) { > + /* Need to figure out how to handle sw for gk20a */ > + if (device->chipset == 0xea) > + got...

...struct nouveau_mm tags; struct nouveau_mm_node *tag_ram; }; @@ -117,10 +118,6 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv) u32 tag_size, tag_margin, tag_align; int ret; - nv_wr32(priv, 0x17e8d8, priv->part_nr); - if (nv_device(pfb)->card_type >= NV_E0) - nv_wr32(priv, 0x17e000, priv->part_nr); - /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */ priv->num_tags = (pfb->ram->size >> 17) / 4; if (priv->num_tags > (1 << 17)) @@ -142,7 +139,7 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, stru...

...struct nouveau_mm tags; struct nouveau_mm_node *tag_ram; }; @@ -117,10 +118,6 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv) u32 tag_size, tag_margin, tag_align; int ret; - nv_wr32(priv, 0x17e8d8, priv->part_nr); - if (nv_device(pfb)->card_type >= NV_E0) - nv_wr32(priv, 0x17e000, priv->part_nr); - /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */ priv->num_tags = (pfb->ram->size >> 17) / 4; if (priv->num_tags > (1 << 17)) @@ -152,7 +149,7 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, stru...

...gt; }; > > @@ -117,10 +118,6 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv) > u32 tag_size, tag_margin, tag_align; > int ret; > > - nv_wr32(priv, 0x17e8d8, priv->part_nr); > - if (nv_device(pfb)->card_type >= NV_E0) > - nv_wr32(priv, 0x17e000, priv->part_nr); > - > /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */ > priv->num_tags = (pfb->ram->size >> 17) / 4; > if (priv->num_tags > (1 << 17)) > @@ -152,7...

...u_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -171,6 +171,11 @@ nouveau_accel_init(struct nouveau_drm *drm) return; } + if (device->chipset == 0xea) { + /* gk20a does not have CE0/CE1 */ + arg0 = NVE0_CHANNEL_IND_ENGINE_GR; + arg1 = 1; + } else if (device->card_type >= NV_E0) { ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, NVDRM_CHAN + 1, @@ -207,6 +212,10 @@ nouveau_accel_init(struct nouveau_drm *drm) return; } + /* Need to figure out how to handle sw for gk20a */ + if (device->chipset == 0xea) + goto skip_sw_init; + ret = n...

...u_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -171,6 +171,11 @@ nouveau_accel_init(struct nouveau_drm *drm) return; } + if (device->chipset == 0xea) { + /* gk20a does not have CE0/CE1 */ + arg0 = NVE0_CHANNEL_IND_ENGINE_GR; + arg1 = 1; + } else if (device->card_type >= NV_E0) { ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, NVDRM_CHAN + 1, @@ -207,6 +212,10 @@ nouveau_accel_init(struct nouveau_drm *drm) return; } + /* Need to figure out how to handle sw for gk20a */ + if (device->chipset == 0xea) + goto skip_sw_init; + ret = n...

...ode should continue on without the channel happily. Perhaps we can just punt the relevent error messages to a debug loglevel for now? > >> + arg0 = NVE0_CHANNEL_IND_ENGINE_GR; >> + arg1 = 1; >> + } else >> if (device->card_type >= NV_E0) { > > The formatting here is somewhat weird. From a brief look I couldn't find > any indication that nouveau deviates from the standard coding style, so > this should be: > > } else if (...) { I use the former in a few places, despite it not entirely being "corre...

...punt the relevent error messages to a debug loglevel for now? Sure, that would be more future-proof as well. > >> >>> + arg0 = NVE0_CHANNEL_IND_ENGINE_GR; >>> + arg1 = 1; >>> + } else >>> if (device->card_type >= NV_E0) { >> >> The formatting here is somewhat weird. From a brief look I couldn't find >> any indication that nouveau deviates from the standard coding style, so >> this should be: >> >> } else if (...) { > I use the former in a few places, despite it n...

.../software/nvc0.c index d698e71..d1f52c0 100644 --- a/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c @@ -80,7 +80,7 @@ nvc0_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd, if ((nv_device(object)->card_type < NV_E0 && crtc > 1) || crtc > 3) return -EINVAL; - nouveau_event_get(disp->vblank, crtc, &chan->base.vblank.event); + nouveau_event_get(disp->vblank, crtc, &chan->base.vblank.event[crtc]); return 0; } @@ -147,7 +147,7 @@ static int nvc0_software_vblsem_release(...

....poll = drm_poll, .fasync = drm_fasync, diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index d120baf..ad146e7 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -704,9 +704,25 @@ enum nouveau_card_type { NV_E0 = 0xe0, }; +struct intr_rwsem { + struct rw_semaphore rwsem; + struct mutex mutex; +}; + +extern void intr_rwsem_init(struct intr_rwsem *r); +extern int intr_rwsem_down_read_interruptible(struct intr_rwsem *r); +extern void intr_rwsem_up_read(struct intr_rwsem *r); +extern void intr_rwsem_...

...vobj_ctor(struct nouveau_object *parent, case NV_30: ret = nv30_identify(device); break; case NV_40: ret = nv40_identify(device); break; case NV_50: ret = nv50_identify(device); break; +#ifdef CONFIG_DRM_NOUVEAU_NVC0 case NV_C0: case NV_D0: ret = nvc0_identify(device); break; case NV_E0: ret = nve0_identify(device); break; +#endif default: ret = -EINVAL; break; diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 9c9ce4d..875c6a0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@...

Hello all, this series includes a wide range of fixes - from a few month's old one-liners from Andreas Heider regarding vga_switcheroo, via a null pointer dereference and double memory allocation, to a buffer overflow. Please review and comment --- drivers/gpu/drm/nouveau/nouveau_acpi.c | 3 ++- drivers/gpu/drm/nouveau/nouveau_device.c | 26 +++++++++++++++-----------

...; case NV_40: ret = nv40_identify(device); break; > case NV_50: ret = nv50_identify(device); break; > +#ifdef CONFIG_DRM_NOUVEAU_NVC0 > case NV_C0: > case NV_D0: ret = nvc0_identify(device); break; > case NV_E0: ret = nve0_identify(device); break; > +#endif > default: > ret = -EINVAL; > break; > diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c > index 9c9ce4d..875c6a0 100644 > ---...

This series was originally motivated by a deadlock, introduced in commit 1d7c71a3e2f77336df536855b0efd2dc5bdeb41b 'drm/nouveau/disp: port vblank handling to event interface', due to inverted lock order between nouveau_drm_vblank_enable() and nouveau_drm_vblank_handler() (the complete lockdep report is included in the patch 4/5 changelog). Because this series fixes the vblank event

Hi everyone, Here is the second batch of patches to add GK20A support to Nouveau. This time we are adding the actual chip support, and this series brings the driver to a point where a slightly-tweaked Mesa successfully runs shaders and renders triangles on GBM! Many thanks to Thierry Reding and the people on the #nouveau IRC channel for their help without which we would not have reached this

...NV_30: ret = nv30_identify(device); break; case NV_40: ret = nv40_identify(device); break; +#endif +#ifdef CONFIG_DRM_NOUVEAU_NV50 case NV_50: ret = nv50_identify(device); break; +#endif +#ifdef CONFIG_DRM_NOUVEAU_NVC0 case NV_C0: case NV_D0: ret = nvc0_identify(device); break; case NV_E0: ret = nve0_identify(device); break; +#endif default: ret = -EINVAL; break; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/names.c b/drivers/gpu/drm/nouveau/core/engine/graph/names.c new file mode 100644 index 0000000..abf6fd0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engi...

Hello everyone, GK20A is the Kepler-based GPU used in the upcoming Tegra K1 chips. The following patches perform architectural changes to Nouveau that are necessary to support non-PCI GPUs and add initial support for GK20A. Although the support is still very basic and more user-space changes will be needed to make the full graphics stack run on top of it, we were able to successfully open