search for: nv_device_base

...ruct drm_device *dev; + struct device *pdev; unsigned i; int r; bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); @@ -1358,6 +1359,7 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm) drm = nouveau_bdev(ttm->bdev); device = nv_device(drm->device); dev = drm->dev; + pdev = nv_device_base(device); #if __OS_HAS_AGP if (drm->agp.stat == ENABLED) { @@ -1377,17 +1379,22 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm) } for (i = 0; i < ttm->num_pages; i++) { - ttm_dma->dma_address[i] = nv_device_map_page(device, - ttm->pages[i]); - if (!ttm_dma->d...

...dev; > unsigned i; > int r; > bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); > @@ -1358,6 +1359,7 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm) > drm = nouveau_bdev(ttm->bdev); > device = nv_device(drm->device); > dev = drm->dev; > + pdev = nv_device_base(device); > > #if __OS_HAS_AGP > if (drm->agp.stat == ENABLED) { > @@ -1377,17 +1379,22 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm) > } > > for (i = 0; i < ttm->num_pages; i++) { > - ttm_dma->dma_address[i] = nv_device_map_page(device, > -...

...const struct firmware *fw; > - char f[32]; > - int ret; > + char f[64]; > + int ret = -EINVAL; > + int i; > > - snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname); > - ret = request_firmware(&fw, f, nv_device_base(device)); > - if (ret) { > - snprintf(f, sizeof(f), "nouveau/%s", fwname); > - ret = request_firmware(&fw, f, nv_device_base(device)); > - if (ret) { > - nv_error(priv, "failed to load %s\n"...

...+ + ret = nv50_fb_create(parent, engine, oclass, data, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv = (struct nvaa_fb_priv *)(*pobject); + + priv->r100c18_page = alloc_page(GFP_KERNEL | __GFP_ZERO); + if (priv->r100c18_page) { + priv->r100c18 = dma_map_page(nv_device_base(device), + priv->r100c18_page, 0, PAGE_SIZE, + DMA_BIDIRECTIONAL); + if (dma_mapping_error(nv_device_base(device), priv->r100c18)) + return -EFAULT; + } else { + nv_warn(priv, "failed 0x100c18 page alloc\n"); + } + return 0; +} + +void +nvaa_fb_dtor(struct nouv...

...vers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c [...] > + pages = dma_alloc_from_contiguous(dev, ncmin, order); > + if (!pages) { > + gk20a_ram_put(pfb, &mem); > + return -ENOMEM; > + } > + > + dma_addr = pfn_to_dma(nv_device_base(nv_device(pfb)), > + page_to_pfn(pages)); This breaks compilation on x86 because neither pfn_to_dma() nor dma_to_pfn() are available. Is there some other way this can be allocated so that these functions don't need to be called? Thierry -------------- next part -------------- A no...

Signed-off-by: Pierre Moreau <pierre.morrow at free.fr> --- drm/nouveau_drm.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drm/nouveau_drm.c b/drm/nouveau_drm.c index afb93bb..ffa1e4f 100644 --- a/drm/nouveau_drm.c +++ b/drm/nouveau_drm.c @@ -61,9 +61,10 @@ MODULE_PARM_DESC(debug, "debug string to pass to driver core"); static char

...loc_from_contiguous(dev, ncmin, order); >>> + if (!pages) { >>> + gk20a_ram_put(pfb, &mem); >>> + return -ENOMEM; >>> + } >>> + >>> + dma_addr = pfn_to_dma(nv_device_base(nv_device(pfb)), >>> + page_to_pfn(pages)); >> >> >> This breaks compilation on x86 because neither pfn_to_dma() nor >> dma_to_pfn() are available. Is there some other way this can be >> allocated so that these functions don...

Hello everyone, GM20B is the GPU of the upcoming Tegra X1 SoC. This series adds initial support for it, based on a rework of the already-supported GK20A. It also introduces support for NVIDIA-provided firmware files, which is why I have added a few NVIDIA people who are relevant to this discussion. The first patch adds support for loading the FECS and GPCCS firmwares from firmware files

...+ + ret = nv50_fb_create(parent, engine, oclass, data, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + priv = (struct nvaa_fb_priv *)(*pobject); + + priv->r100c18_page = alloc_page(GFP_KERNEL | __GFP_ZERO); + if (priv->r100c18_page) { + priv->r100c18 = dma_map_page(nv_device_base(device), + priv->r100c18_page, 0, PAGE_SIZE, + DMA_BIDIRECTIONAL); + if (dma_mapping_error(nv_device_base(device), priv->r100c18)) + return -EFAULT; + } else { + nv_warn(priv, "failed 0x100c18 page alloc\n"); + } + return 0; +} + +void +nvaa_fb_dtor(struct nouv...

It has been a couple of months since v4 - apologies for this. v4 has not received many comments, but this version addresses them and makes a new attempt at pushing the critical bit for GK20A and Nouveau on ARM in general. As a reminder, this series addresses the memory coherency issue that we are seeing on ARM platforms. Contrary to x86 which invalidates the PCI caches whenever a write is made by

...+119,7 @@ _nouveau_falcon_init(struct nouveau_object *object) snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03x", device->chipset, falcon->addr >> 12); - ret = request_firmware(&fw, name, &device->pdev->dev); + ret = request_firmware(&fw, name, nv_device_base(device)); if (ret == 0) { falcon->code.data = vmemdup(fw->data, fw->size); falcon->code.size = fw->size; @@ -138,7 +138,7 @@ _nouveau_falcon_init(struct nouveau_object *object) snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xd", device->chipset, fa...

...9 +23,17 @@ #include <core/device.h> -struct gk20a_mem { - struct nvkm_mem base; - void *cpuaddr; - dma_addr_t handle; -}; -#define to_gk20a_mem(m) container_of(m, struct gk20a_mem, base) - static void gk20a_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem) { - struct device *dev = nv_device_base(nv_device(pfb)); - struct gk20a_mem *mem = to_gk20a_mem(*pmem); - - *pmem = NULL; - if (unlikely(mem == NULL)) - return; - - if (likely(mem->cpuaddr)) - dma_free_coherent(dev, mem->base.size << PAGE_SHIFT, - mem->cpuaddr, mem->handle); - - kfree(mem->base.pages); - kfree...

...priv); > + if (ret) > + return ret; > + > + priv = (struct nvaa_fb_priv *)(*pobject); > + > + priv->r100c18_page = alloc_page(GFP_KERNEL | __GFP_ZERO); > + if (priv->r100c18_page) { > + priv->r100c18 = dma_map_page(nv_device_base(device), > + priv->r100c18_page, 0, PAGE_SIZE, > + DMA_BIDIRECTIONAL); > + if (dma_mapping_error(nv_device_base(device), priv->r100c18)) > + return -EFAULT; &g...

...; + struct ttm_tt *ttm = nvbo->bo.ttm; > + > + device = nouveau_dev(nouveau_bdev(ttm->bdev)->dev); > + > + if (nvbo->bo.ttm && nvbo->bo.ttm->caching_state == tt_cached) > + ttm_dma_tt_cache_sync_for_cpu((struct ttm_dma_tt *)nvbo->bo.ttm, > + nv_device_base(device)); Can we be certain at this point that the struct ttm_tt is in fact a struct ttm_dma_tt? > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h [...] > +#if IS_ENABLED(CONFIG_ARCH_TEGRA) > +#define NOUVEAU_NEED_CACHE_SYNC > +#endif I know I...

...struct nouveau_device *device; + struct ttm_tt *ttm = nvbo->bo.ttm; + + device = nouveau_dev(nouveau_bdev(ttm->bdev)->dev); + + if (nvbo->bo.ttm && nvbo->bo.ttm->caching_state == tt_cached) + ttm_dma_tt_cache_sync_for_cpu((struct ttm_dma_tt *)nvbo->bo.ttm, + nv_device_base(device)); +} + +void +nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) +{ + struct ttm_tt *ttm = nvbo->bo.ttm; + + if (ttm && ttm->caching_state == tt_cached) { + struct nouveau_device *device; + + device = nouveau_dev(nouveau_bdev(ttm->bdev)->dev); + + ttm_dma_tt_cache_sy...

...(nv_device_is_pci(device)) { + for (i = 0; i < ttm_dma->ttm.num_pages; i++) + pci_dma_sync_single_for_device(device->pdev, + ttm_dma->dma_address[i], PAGE_SIZE, + PCI_DMA_TODEVICE); + } else { + for (i = 0; i < ttm_dma->ttm.num_pages; i++) + dma_sync_single_for_device(nv_device_base(device), + ttm_dma->dma_address[i], PAGE_SIZE, + DMA_TO_DEVICE); + } +} + +void +nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) +{ + struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); + struct nouveau_device *device = nouveau_dev(drm->dev); + struct ttm_dma_tt *ttm_dma = (struc...

On 12/02/14 05:38, Alexandre Courbot wrote: > Upcoming mobile Kepler GPUs (such as GK20A) use the platform bus instead > of PCI to which Nouveau is tightly dependent. This patch allows Nouveau > to handle platform devices by: > > - abstracting PCI-dependent functions that were typically used for > resource querying and page mapping, > - introducing a nv_device_is_pci()

...NGS IN THE SOFTWARE. + */ + +#include "priv.h" + +#include <subdev/fb.h> + +#include <linux/mm.h> +#include <linux/types.h> +#include <linux/dma-contiguous.h> + +static void +gk20a_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) +{ + struct device *dev = nv_device_base(nv_device(pfb)); + struct nouveau_mem *mem = *pmem; + int i; + + *pmem = NULL; + + for (i = 0; i < mem->size; i++) { + struct page *page; + + if (mem->pages[i] == 0) + break; + + page = pfn_to_page(dma_to_pfn(dev, mem->pages[i])); + dma_release_from_contiguous(dev, page, 1); + } +...

...d -gk20a_instobj_dtor(struct nvkm_object *object) +gk20a_instobj_dtor_dma(struct gk20a_instobj_priv *_node) { - struct gk20a_instobj_priv *node = (void *)object; + struct gk20a_instobj_dma *node = (void *)_node; struct gk20a_instmem_priv *priv = (void *)nvkm_instmem(node); struct device *dev = nv_device_base(nv_device(priv)); if (unlikely(!node->handle)) return; - dma_free_attrs(dev, node->mem->size << PAGE_SHIFT, node->cpuaddr, + dma_free_attrs(dev, _node->mem->size << PAGE_SHIFT, node->cpuaddr, node->handle, &node->attrs); +} + +static voi...

On Mon, Feb 10, 2014 at 8:50 PM, Thierry Reding <thierry.reding at gmail.com> wrote: > On Mon, Feb 10, 2014 at 02:53:00PM +0900, Alexandre Courbot wrote: > [...] >> diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c > [...] >> +resource_size_t >> +nv_device_resource_start(struct nouveau_device *device,