search for: nv_cpu_cache_flush_area

...ore/os.h > index d0ced94ca54c..274b4460bb03 100644 > --- a/drivers/gpu/drm/nouveau/core/os.h > +++ b/drivers/gpu/drm/nouveau/core/os.h > @@ -38,4 +38,21 @@ > #endif /* def __BIG_ENDIAN else */ > #endif /* !ioread32_native */ > > +#if defined(__arm__) > + > +#define nv_cpu_cache_flush_area(va, size) \ > +do { \ > + phys_addr_t pa = virt_to_phys(va); \ > + __cpuc_flush_dcache_area(va, size); \ > + outer_flush_range(pa, pa + size); \ > +} while (0) Couldn't this be a static inline function? > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/d...

.../drm/nouveau/core/os.h b/drivers/gpu/drm/nouveau/core/os.h index d0ced94ca54c..274b4460bb03 100644 --- a/drivers/gpu/drm/nouveau/core/os.h +++ b/drivers/gpu/drm/nouveau/core/os.h @@ -38,4 +38,21 @@ #endif /* def __BIG_ENDIAN else */ #endif /* !ioread32_native */ +#if defined(__arm__) + +#define nv_cpu_cache_flush_area(va, size) \ +do { \ + phys_addr_t pa = virt_to_phys(va); \ + __cpuc_flush_dcache_area(va, size); \ + outer_flush_range(pa, pa + size); \ +} while (0) + +#else + +#define nv_cpu_cache_flush_area(va, size) \ +do { \ +} while (0) + +#endif /* defined(__arm__) */ + #endif diff --git a/driver...

...rs/gpu/drm/nouveau/core/os.h >> > +++ b/drivers/gpu/drm/nouveau/core/os.h >> > @@ -38,4 +38,21 @@ >> > #endif /* def __BIG_ENDIAN else */ >> > #endif /* !ioread32_native */ >> > >> > +#if defined(__arm__) >> > + >> > +#define nv_cpu_cache_flush_area(va, size) \ >> > +do { \ >> > + phys_addr_t pa = virt_to_phys(va); \ >> > + __cpuc_flush_dcache_area(va, size); \ >> > + outer_flush_range(pa, pa + size); \ >> > +} while (0) >> &g...

...ouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) > > > mem = &mem[index]; > > > if (is_iomem) > > > iowrite16_native(val, (void __force __iomem *)mem); > > > - else > > > + else { > > > *mem = val; > > > + nv_cpu_cache_flush_area(mem, 2); > > > + } > > > } > > > > > > u32 > > > @@ -461,8 +463,10 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) > > > mem = &mem[index]; > > > if (is_iomem) > > > iowrite32_native(val, (vo...

...3 100644 > > --- a/drivers/gpu/drm/nouveau/core/os.h > > +++ b/drivers/gpu/drm/nouveau/core/os.h > > @@ -38,4 +38,21 @@ > > #endif /* def __BIG_ENDIAN else */ > > #endif /* !ioread32_native */ > > > > +#if defined(__arm__) > > + > > +#define nv_cpu_cache_flush_area(va, size) \ > > +do { \ > > + phys_addr_t pa = virt_to_phys(va); \ > > + __cpuc_flush_dcache_area(va, size); \ > > + outer_flush_range(pa, pa + size); \ > > +} while (0) > > Couldn't this be a static inline function? > > > diff --git a/drivers...

This small series introduces TTM helper functions as well as Nouveau hooks that are needed to ensure buffer coherency on ARM. Most of this series is a forward-port of some patches Lucas Stach sent last year and that are also needed for Nouveau GK20A support: http://lists.freedesktop.org/archives/nouveau/2013-August/014026.html Another patch takes care of flushing the CPU write-buffer when

...;>> > +++ b/drivers/gpu/drm/nouveau/core/os.h >>> > @@ -38,4 +38,21 @@ >>> > #endif /* def __BIG_ENDIAN else */ >>> > #endif /* !ioread32_native */ >>> > >>> > +#if defined(__arm__) >>> > + >>> > +#define nv_cpu_cache_flush_area(va, size) \ >>> > +do { \ >>> > + phys_addr_t pa = virt_to_phys(va); \ >>> > + __cpuc_flush_dcache_area(va, size); \ >>> > + outer_flush_range(pa, pa + size); \ >>> > +} w...