search for: nv_clk_src_gpc

...uveau_volt *); > diff --git a/nvkm/subdev/clock/gk20a.c b/nvkm/subdev/clock/gk20a.c > index 82abbea2be12..fb4fad374bdd 100644 > --- a/nvkm/subdev/clock/gk20a.c > +++ b/nvkm/subdev/clock/gk20a.c > @@ -470,76 +470,91 @@ gk20a_pstates[] = { > { > .base = { > .domain[nv_clk_src_gpc] = 72000, > + .voltage = 0, > }, > }, > { > .base = { > .domain[nv_clk_src_gpc] = 108000, > + .voltage = 1, > }, > }, > { > .base = { > .domain[nv_clk_src_gpc] = 180000, > + .voltage = 2, > }, > }, >...

...lock/gk20a.c >>> index 82abbea2be12..fb4fad374bdd 100644 >>> --- a/nvkm/subdev/clock/gk20a.c >>> +++ b/nvkm/subdev/clock/gk20a.c >>> @@ -470,76 +470,91 @@ gk20a_pstates[] = { >>> { >>> .base = { >>> .domain[nv_clk_src_gpc] = 72000, >>> + .voltage = 0, >>> }, >>> }, >>> { >>> .base = { >>> .domain[nv_clk_src_gpc] = 108000, >>> + .voltage = 1, >>> }, >>> }...

...; index 82abbea2be12..fb4fad374bdd 100644 >>>> --- a/nvkm/subdev/clock/gk20a.c >>>> +++ b/nvkm/subdev/clock/gk20a.c >>>> @@ -470,76 +470,91 @@ gk20a_pstates[] = { >>>> { >>>> .base = { >>>> .domain[nv_clk_src_gpc] = 72000, >>>> + .voltage = 0, >>>> }, >>>> }, >>>> { >>>> .base = { >>>> .domain[nv_clk_src_gpc] = 108000, >>>> + .voltage = 1, >>>>...

...olt *); int nouveau_voltgpio_get(struct nouveau_volt *); diff --git a/nvkm/subdev/clock/gk20a.c b/nvkm/subdev/clock/gk20a.c index 82abbea2be12..fb4fad374bdd 100644 --- a/nvkm/subdev/clock/gk20a.c +++ b/nvkm/subdev/clock/gk20a.c @@ -470,76 +470,91 @@ gk20a_pstates[] = { { .base = { .domain[nv_clk_src_gpc] = 72000, + .voltage = 0, }, }, { .base = { .domain[nv_clk_src_gpc] = 108000, + .voltage = 1, }, }, { .base = { .domain[nv_clk_src_gpc] = 180000, + .voltage = 2, }, }, { .base = { .domain[nv_clk_src_gpc] = 252000, + .voltage = 3, }, }, { ....

...olt *); int nouveau_voltgpio_get(struct nouveau_volt *); diff --git a/nvkm/subdev/clock/gk20a.c b/nvkm/subdev/clock/gk20a.c index 82abbea2be12..fb4fad374bdd 100644 --- a/nvkm/subdev/clock/gk20a.c +++ b/nvkm/subdev/clock/gk20a.c @@ -470,76 +470,91 @@ gk20a_pstates[] = { { .base = { .domain[nv_clk_src_gpc] = 72000, + .voltage = 0, }, }, { .base = { .domain[nv_clk_src_gpc] = 108000, + .voltage = 1, }, }, { .base = { .domain[nv_clk_src_gpc] = 180000, + .voltage = 2, }, }, { .base = { .domain[nv_clk_src_gpc] = 252000, + .voltage = 3, }, }, { ....

Some Tegra drivers might be complied as kernel modules, and they need the fuse information for initialization. One example is the GK20A Nouveau driver. It needs the GPU speedo value to calculate frequency-voltage table. So export the tegra_sku_info. Signed-off-by: Vince Hsu <vinceh at nvidia.com> --- v2: add more description why we need this patch drivers/soc/tegra/fuse/fuse-tegra.c | 1

...lock/gk20a.c b/nvkm/subdev/clock/gk20a.c >> index 82abbea2be12..fb4fad374bdd 100644 >> --- a/nvkm/subdev/clock/gk20a.c >> +++ b/nvkm/subdev/clock/gk20a.c >> @@ -470,76 +470,91 @@ gk20a_pstates[] = { >> { >> .base = { >> .domain[nv_clk_src_gpc] = 72000, >> + .voltage = 0, >> }, >> }, >> { >> .base = { >> .domain[nv_clk_src_gpc] = 108000, >> + .voltage = 1, >> }, >> }, >> { >>...

Signed-off-by: Vince Hsu <vinceh at nvidia.com> --- nvkm/subdev/volt/base.c | 67 ++++++++++++++++++++++++++++--------------------- 1 file changed, 38 insertions(+), 29 deletions(-) diff --git a/nvkm/subdev/volt/base.c b/nvkm/subdev/volt/base.c index 32794a999106..26ccd8df193f 100644 --- a/nvkm/subdev/volt/base.c +++ b/nvkm/subdev/volt/base.c @@ -101,6 +101,41 @@ nouveau_volt_set_id(struct

...k20a_pllg_slide(priv, n_lo); + } + + /* put PLL in bypass before disabling it */ + nv_mask(priv, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); + + _gk20a_pllg_disable(priv); +} + +#define GK20A_CLK_GPC_MDIV 1000 + +static struct nouveau_clocks +gk20a_domains[] = { + { nv_clk_src_crystal, 0xff }, + { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, + { nv_clk_src_max } +}; + +static struct nouveau_pstate +gk20a_pstates[] = { + { + .base = { + .domain[nv_clk_src_gpc] = 72000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 108000, + }, + }, + { + .base = { + .domain[nv_clk_src_...

Some Tegra drivers might be compiled as kernel modules, and they need the fuse information for initialization. One example is the GK20A Nouveau driver. It needs the GPU speedo value to calculate frequency-voltage table. So export the tegra_sku_info. Signed-off-by: Vince Hsu <vinceh at nvidia.com> Acked-by: Alexandre Courbot <acourbot at nvidia.com> Acked-by: Thierry Reding <treding

Some Tegra drivers might be compiled as kernel modules, and they need the fuse information for initialization. One example is the GK20A Nouveau driver. It needs the GPU speedo value to calculate frequency-voltage table. So export the tegra_sku_info. Signed-off-by: Vince Hsu <vinceh at nvidia.com> Acked-by: Alexandre Courbot <acourbot at nvidia.com> Acked-by: Thierry Reding <treding

...ss before disabling it */ > + nv_mask(priv, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); > + > + _gk20a_pllg_disable(priv); > +} > + > +#define GK20A_CLK_GPC_MDIV 1000 > + > +static struct nouveau_clocks > +gk20a_domains[] = { > + { nv_clk_src_crystal, 0xff }, > + { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, > + { nv_clk_src_max } > +}; > + > +static struct nouveau_pstate > +gk20a_pstates[] = { > + { > + .base = { > + .domain[nv_clk_src_gpc] = 72000, > + }, > + }, > + { > + .base = { > + .domain[nv_clk_src_g...

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

...gf100.c > index a52b7e7..eaf4f83 100644 > --- a/drm/nouveau/nvkm/subdev/clk/gf100.c > +++ b/drm/nouveau/nvkm/subdev/clk/gf100.c > @@ -443,7 +443,7 @@ gf100_clk = { > { nv_clk_src_hubk06 , 0x00 }, > { nv_clk_src_hubk01 , 0x01 }, > { nv_clk_src_copy , 0x02 }, > - { nv_clk_src_gpc , 0x03, 0, "core", 2000 }, > + { nv_clk_src_gpc , 0x03, NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE, "core", 2000 }, > { nv_clk_src_rop , 0x04 }, > { nv_clk_src_mem , 0x05, 0, "memory", 1000 }, > { nv_clk_src_vdec , 0x06 }, > diff --git a/d...

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wrong in terms of integration to your tree, as the main purpose of

...k/gf100.c b/drm/nouveau/nvkm/subdev/clk/gf100.c index a52b7e7..eaf4f83 100644 --- a/drm/nouveau/nvkm/subdev/clk/gf100.c +++ b/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -443,7 +443,7 @@ gf100_clk = { { nv_clk_src_hubk06 , 0x00 }, { nv_clk_src_hubk01 , 0x01 }, { nv_clk_src_copy , 0x02 }, - { nv_clk_src_gpc , 0x03, 0, "core", 2000 }, + { nv_clk_src_gpc , 0x03, NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE, "core", 2000 }, { nv_clk_src_rop , 0x04 }, { nv_clk_src_mem , 0x05, 0, "memory", 1000 }, { nv_clk_src_vdec , 0x06 }, diff --git a/drm/nouveau/nvkm/subdev/cl...

...k/gf100.c b/drm/nouveau/nvkm/subdev/clk/gf100.c index 78c449b..71b7c9f 100644 --- a/drm/nouveau/nvkm/subdev/clk/gf100.c +++ b/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -443,7 +443,7 @@ gf100_clk = { { nv_clk_src_hubk06 , 0x00 }, { nv_clk_src_hubk01 , 0x01 }, { nv_clk_src_copy , 0x02 }, - { nv_clk_src_gpc , 0x03, 0, "core", 2000 }, + { nv_clk_src_gpc , 0x03, NVKM_CLK_DOM_FLAG_BASECLK, "core", 2000 }, { nv_clk_src_rop , 0x04 }, { nv_clk_src_mem , 0x05, 0, "memory", 1000 }, { nv_clk_src_vdec , 0x06 }, diff --git a/drm/nouveau/nvkm/subdev/clk/gk104....

...therm = device->therm; + volt = device->volt; + + printf("current voltage (µV), expected voltage (µV), abs diff (µV)," + "rel diff nouveau/nvidia (%%), pstate, cstate, temperature" + "(°C)\n"); + while (true) { + int gpc_clock = nvkm_clk_read(clk, nv_clk_src_gpc); + int mem_clock = nvkm_clk_read(clk, nv_clk_src_mem); + struct nvkm_pstate *pstate = NULL, *best_pstate = NULL; + struct nvkm_cstate *cstate = NULL, *best_cstate = NULL; + int mem_err, gpc_err; + int new_voltage, new_nouveau_voltage, new_pstate, new_cstate; + int new_temp; + + list_for_eac...

...k/gf100.c b/drm/nouveau/nvkm/subdev/clk/gf100.c index 78c449b..71b7c9f 100644 --- a/drm/nouveau/nvkm/subdev/clk/gf100.c +++ b/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -443,7 +443,7 @@ gf100_clk = { { nv_clk_src_hubk06 , 0x00 }, { nv_clk_src_hubk01 , 0x01 }, { nv_clk_src_copy , 0x02 }, - { nv_clk_src_gpc , 0x03, 0, "core", 2000 }, + { nv_clk_src_gpc , 0x03, NVKM_CLK_DOM_FLAG_BASECLK, "core", 2000 }, { nv_clk_src_rop , 0x04 }, { nv_clk_src_mem , 0x05, 0, "memory", 1000 }, { nv_clk_src_vdec , 0x06 }, diff --git a/drm/nouveau/nvkm/subdev/clk/gk104....

...7e7..eaf4f83 100644 > > --- a/drm/nouveau/nvkm/subdev/clk/gf100.c > > +++ b/drm/nouveau/nvkm/subdev/clk/gf100.c > > @@ -443,7 +443,7 @@ gf100_clk = { > > { nv_clk_src_hubk06 , 0x00 }, > > { nv_clk_src_hubk01 , 0x01 }, > > { nv_clk_src_copy , 0x02 }, > > - { nv_clk_src_gpc , 0x03, 0, "core", 2000 }, > > + { nv_clk_src_gpc , 0x03, NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE, "core", 2000 > > }, > > { nv_clk_src_rop , 0x04 }, > > { nv_clk_src_mem , 0x05, 0, "memory", 1000 }, > > { nv_clk_src_vdec , 0x06 }, > > dif...