search for: nv_clk_src

Following a series of patches to improve nouveaus clock tree parsing. Reclocking these engines (all but memory) is pretty stable on the cards I've tested. Please review and merge when approved. These patches do not solve the problem that core/shader engine doesn't like to be clocked up too far without fb following, with visible corruption as a result. I suspect this problem is unrelated

...nit_oclass; diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h index e2675bc..8f4ced7 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h @@ -14,6 +14,9 @@ enum nv_clk_src { nv_clk_src_hclk, nv_clk_src_hclkm3, nv_clk_src_hclkm3d2, + nv_clk_src_hclkm2d3, /* NVAA */ + nv_clk_src_hclkm4, /* NVAA */ + nv_clk_src_cclk, /* NVAA */ nv_clk_src_host, @@ -127,6 +130,7 @@ extern struct nouveau_oclass nv04_clock_oclass; extern struct nouveau_oclass nv40_clock_oclass...

...nit_oclass; diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h index e2675bc..8f4ced7 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h @@ -14,6 +14,9 @@ enum nv_clk_src { nv_clk_src_hclk, nv_clk_src_hclkm3, nv_clk_src_hclkm3d2, + nv_clk_src_hclkm2d3, /* NVAA */ + nv_clk_src_hclkm4, /* NVAA */ + nv_clk_src_cclk, /* NVAA */ nv_clk_src_host, @@ -127,6 +130,7 @@ extern struct nouveau_oclass nv04_clock_oclass; extern struct nouveau_oclass nv40_clock_oclass...

Reclocking of NVAA/NVAC is substantially different from NV50+, enough to justify a separate clock implementation. This code is a forward-port of reclocking code that has been sitting in a branch for a while, and has been tested on my NVAC. Traces show no significant reasons why this shouldn't work on NVAA, but testers are always welcome. And since these are IGPs without dedicated RAM to

...git a/drm/nouveau/include/nvkm/subdev/clk.h b/drm/nouveau/include/nvkm/subdev/clk.h > index 8708f0a..8085d81 100644 > --- a/drm/nouveau/include/nvkm/subdev/clk.h > +++ b/drm/nouveau/include/nvkm/subdev/clk.h > @@ -64,7 +64,8 @@ struct nvkm_pstate { > struct nvkm_domain { > enum nv_clk_src name; > u8 bios; /* 0xff for none */ > -#define NVKM_CLK_DOM_FLAG_CORE 0x01 > +#define NVKM_CLK_DOM_FLAG_CORE 0x01 > +#define NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE 0x02 > u8 flags; > const char *mname; > int mdiv; > @@ -94,6 +95,13 @@ struct nvkm_clk { >...

...ers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c index da1770e47490..ae2733035ac2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c @@ -313,6 +313,7 @@ nv50_clk_read(struct nvkm_clk *base, enum nv_clk_src src) default: break; } + break; default: break; } -- 2.27.0

...1 disabled, -2 perfmon) */ int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */ int astate; /* perfmon adjustment (base) */ - int dstate; /* display adjustment (min+) */ u8 temp; bool allow_reclock; @@ -121,7 +120,6 @@ struct nvkm_clk { int nvkm_clk_read(struct nvkm_clk *, enum nv_clk_src); int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr); int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait); -int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel); int nvkm_clk_tstate(struct nvkm_clk *, u8 temperature); int nvkm_clk_update(struct nvkm_clk *clk, bool wait...

...1 disabled, -2 perfmon) */ int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */ int astate; /* perfmon adjustment (base) */ - int dstate; /* display adjustment (min+) */ u8 temp; bool allow_reclock; @@ -121,7 +120,6 @@ struct nvkm_clk { int nvkm_clk_read(struct nvkm_clk *, enum nv_clk_src); int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr); int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait); -int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel); int nvkm_clk_tstate(struct nvkm_clk *, u8 temperature); int nvkm_clk_update(struct nvkm_clk *, bool wait);...

...vkm/subdev/clk.h > +++ b/drm/nouveau/include/nvkm/subdev/clk.h > @@ -10,6 +10,8 @@ struct nvkm_pll_vals; > #define NVKM_CLK_CSTATE_BASE -2 /* pstate base */ > #define NVKM_CLK_CSTATE_HIGHEST -3 /* highest possible */ > > +#define NVKM_CLK_PSTATE_DEFAULT -1 > + > enum nv_clk_src { > nv_clk_src_crystal, > nv_clk_src_href, > @@ -95,7 +97,7 @@ struct nvkm_clk { > > struct nvkm_notify pwrsrc_ntfy; > int pwrsrc; > - int pstate; /* current */ > + struct nvkm_pstate *pstate; /* current */ > int ustate_ac; /* user-requested (-1 disabled, -2 p...

...isabled, -2 perfmon) */ int astate; /* perfmon adjustment (base) */ - int tstate; /* thermal adjustment (max-) */ - int dstate; /* display adjustment (min+) */ bool allow_reclock; #define NVKM_CLK_BOOST_NONE 0x0 @@ -118,8 +116,6 @@ struct nvkm_clk { int nvkm_clk_read(struct nvkm_clk *, enum nv_clk_src); int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr); int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait); -int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel); -int nvkm_clk_tstate(struct nvkm_clk *, int req, int rel); int nvkm_clk_update(struct nvkm_clk *, bool wait)...

...ns(+), 4 deletions(-) diff --git a/drm/nouveau/include/nvkm/subdev/clk.h b/drm/nouveau/include/nvkm/subdev/clk.h index 8708f0a..8085d81 100644 --- a/drm/nouveau/include/nvkm/subdev/clk.h +++ b/drm/nouveau/include/nvkm/subdev/clk.h @@ -64,7 +64,8 @@ struct nvkm_pstate { struct nvkm_domain { enum nv_clk_src name; u8 bios; /* 0xff for none */ -#define NVKM_CLK_DOM_FLAG_CORE 0x01 +#define NVKM_CLK_DOM_FLAG_CORE 0x01 +#define NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE 0x02 u8 flags; const char *mname; int mdiv; @@ -94,6 +95,13 @@ struct nvkm_clk { int dstate; /* display adjustment (min+) */...

...ns(+), 5 deletions(-) diff --git a/drm/nouveau/include/nvkm/subdev/clk.h b/drm/nouveau/include/nvkm/subdev/clk.h index fb54417..a292e5a 100644 --- a/drm/nouveau/include/nvkm/subdev/clk.h +++ b/drm/nouveau/include/nvkm/subdev/clk.h @@ -67,7 +67,8 @@ struct nvkm_pstate { struct nvkm_domain { enum nv_clk_src name; u8 bios; /* 0xff for none */ -#define NVKM_CLK_DOM_FLAG_CORE 0x01 +#define NVKM_CLK_DOM_FLAG_CORE 0x01 +#define NVKM_CLK_DOM_FLAG_BASECLK 0x02 u8 flags; const char *mname; int mdiv; @@ -97,6 +98,12 @@ struct nvkm_clk { int dstate; /* display adjustment (min+) */ bool allow_re...

...* perfmon adjustment (base) */ > - int tstate; /* thermal adjustment (max-) */ > - int dstate; /* display adjustment (min+) */ > > bool allow_reclock; > #define NVKM_CLK_BOOST_NONE 0x0 > @@ -118,8 +116,6 @@ struct nvkm_clk { > int nvkm_clk_read(struct nvkm_clk *, enum nv_clk_src); > int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr); > int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait); > -int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel); > -int nvkm_clk_tstate(struct nvkm_clk *, int req, int rel); > int nvkm_clk_update(s...

...ns(+), 4 deletions(-) diff --git a/drm/nouveau/include/nvkm/subdev/clk.h b/drm/nouveau/include/nvkm/subdev/clk.h index 6226f0d..99ee05c 100644 --- a/drm/nouveau/include/nvkm/subdev/clk.h +++ b/drm/nouveau/include/nvkm/subdev/clk.h @@ -68,7 +68,8 @@ struct nvkm_pstate { struct nvkm_domain { enum nv_clk_src name; u8 bios; /* 0xff for none */ -#define NVKM_CLK_DOM_FLAG_CORE 0x01 +#define NVKM_CLK_DOM_FLAG_CORE 0x01 +#define NVKM_CLK_DOM_FLAG_BASECLK 0x02 u8 flags; const char *mname; int mdiv; @@ -98,6 +99,12 @@ struct nvkm_clk { int dstate; /* display adjustment (min+) */ bool allow_re...

.../clk.h > > b/drm/nouveau/include/nvkm/subdev/clk.h > > index 8708f0a..8085d81 100644 > > --- a/drm/nouveau/include/nvkm/subdev/clk.h > > +++ b/drm/nouveau/include/nvkm/subdev/clk.h > > @@ -64,7 +64,8 @@ struct nvkm_pstate { > > struct nvkm_domain { > > enum nv_clk_src name; > > u8 bios; /* 0xff for none */ > > -#define NVKM_CLK_DOM_FLAG_CORE 0x01 > > +#define NVKM_CLK_DOM_FLAG_CORE 0x01 > > +#define NVKM_CLK_DOM_FLAG_BASE_CLOCK_CORE 0x02 > > u8 flags; > > const char *mname; > > int mdiv; > > @@ -94,6 +95,13 @@ stru...

...63b7f 100644 --- a/drm/nouveau/include/nvkm/subdev/clk.h +++ b/drm/nouveau/include/nvkm/subdev/clk.h @@ -10,6 +10,8 @@ struct nvkm_pll_vals; #define NVKM_CLK_CSTATE_BASE -2 /* pstate base */ #define NVKM_CLK_CSTATE_HIGHEST -3 /* highest possible */ +#define NVKM_CLK_PSTATE_DEFAULT -1 + enum nv_clk_src { nv_clk_src_crystal, nv_clk_src_href, @@ -95,7 +97,7 @@ struct nvkm_clk { struct nvkm_notify pwrsrc_ntfy; int pwrsrc; - int pstate; /* current */ + struct nvkm_pstate *pstate; /* current */ int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */ int ustate_dc; /* user-requested...

...u/drm/nouveau/core/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c index a08011c..b9ab90a 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c @@ -163,17 +163,12 @@ nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) } int -nva3_clock_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz, +nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz, struct nva3_clock_info *info) { - struct nouveau_bios *bios = nouveau_bios(clock); struct nva3_clock_priv *priv = (void *)clock; - struct nvbio...

...37e08 100644 --- a/drm/nouveau/include/nvkm/subdev/clk.h +++ b/drm/nouveau/include/nvkm/subdev/clk.h @@ -10,6 +10,8 @@ struct nvkm_pll_vals; #define NVKM_CLK_CSTATE_BASE -2 /* pstate base */ #define NVKM_CLK_CSTATE_HIGHEST -3 /* highest possible */ +#define NVKM_CLK_PSTATE_DEFAULT -1 + enum nv_clk_src { nv_clk_src_crystal, nv_clk_src_href, @@ -95,7 +97,7 @@ struct nvkm_clk { struct nvkm_notify pwrsrc_ntfy; int pwrsrc; - int pstate; /* current */ + struct nvkm_pstate *pstate; /* current */ int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */ int ustate_dc; /* user-requested...

.../drm/nouveau/nvkm/subdev/clk/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c index efa50274df97..4884eb4a9221 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c @@ -140,17 +140,14 @@ mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src) break; case nv_clk_src_mem: return 0; - break; case nv_clk_src_vdec: P = (read_div(clk) & 0x00000700) >> 8; switch (mast & 0x00400000) { case 0x00400000: return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; - break; default: retu...

...ndex 8f4ced7..c01e29c 100644 --- a/nvkm/include/subdev/clock.h +++ b/nvkm/include/subdev/clock.h @@ -77,6 +77,8 @@ struct nouveau_clock { int tstate; /* thermal adjustment (max-) */ int dstate; /* display adjustment (min+) */ + bool allow_reclock; + int (*read)(struct nouveau_clock *, enum nv_clk_src); int (*calc)(struct nouveau_clock *, struct nouveau_cstate *); int (*prog)(struct nouveau_clock *); @@ -106,8 +108,8 @@ struct nouveau_clocks { int mdiv; }; -#define nouveau_clock_create(p,e,o,i,d) \ - nouveau_clock_create_((p), (e), (o), (i), size...