search for: nv98_bsp_oclass

...; - nv_engine(priv)->cclass = &nv84_bsp_cclass; - nv_engine(priv)->sclass = nv84_bsp_sclass; + nv_engine(priv)->cclass = &nv98_bsp_cclass; + nv_engine(priv)->sclass = nv98_bsp_sclass; return 0; } struct nouveau_oclass -nv84_bsp_oclass = { - .handle = NV_ENGINE(BSP, 0x84), +nv98_bsp_oclass = { + .handle = NV_ENGINE(BSP, 0x98), .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv84_bsp_ctor, + .ctor = nv98_bsp_ctor, .dtor = _nouveau_engine_dtor, .init = _nouveau_engine_init, .fini = _nouveau_engine_fini, diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/dr...

These chipsets include the VP2 engine which is composed of a bitstream processor (BSP) that decodes H.264 and a video processor (VP) which can do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are driven by separate xtensa chips embedded in the hardware. This patch provides the mechanism to load the kernel for the xtensa chips and provide the necessary interactions to do the rest of

...*engine, struct nv98_bsp_priv *priv; int ret; - ret = nouveau_engine_create(parent, engine, oclass, true, + ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true, "PBSP", "bsp", &priv); *pobject = nv_object(priv); if (ret) @@ -86,8 +102,10 @@ nv98_bsp_oclass = { .handle = NV_ENGINE(BSP, 0x98), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nv98_bsp_ctor, - .dtor = _nouveau_engine_dtor, - .init = _nouveau_engine_init, - .fini = _nouveau_engine_fini, + .dtor = _nouveau_falcon_dtor, + .init = nv98_bsp_init, + .fini = _nouveau_falcon_fini, +...